Command and Status Register @0x4

16-bit Command Register and 16-bit Status Register.

Table 1. i_command_status
Bits SW Name Description Reset
0 R/W I/O-Space Enable [ISE] Controls a Function's response to I/O Space accesses received from PCIe Link. The Controller internally uses this bit to respond to received I/O Requests as follows:
  • When this bit is Clear, all received I/O Space accesses are handled as Unsupported Requests.
  • When this bit is Set, all received I/O Space accesses are decoded and processed normally.
This field can be written from the local management bus.		 0x0
1 R/W Mem-Space Enable [MSE] Controls a Function's response to Memory Space accesses received from PCIe Link. The Controller internally uses this bit to respond to received Memory Requests as follows:
  • When this bit is Clear, all received Memory Space accesses are handled as Unsupported Requests.
  • When this bit is Set, all received Memory Space accesses are decoded and processed normally.
This field can be written from the local management bus.		 0x0
2 R/W Bus-Master Enable [BE] Controls the ability of a Function to issue Memory and I/O Read/Write Requests in the Upstream direction. This field can be written from the local management bus.
Note: The Controller does not gate any requests based on this bit. The Client Application logic must use this bit to gate requests as follows:
  • When this bit is Set, the Function is allowed to issue Memory or I/O Requests on the pcie_master_AXI interface.
  • When this bit is Clear, the Function must not be allowed to issue any Memory or I/O Requests on the pcie_master_AXI interface.
 0x0
5:3 R Reserved [R0] Reserved 0x0
6 R/W Parity Error Response Enable [PERE]
When this bit is 1, the Controller sets the Master Data Parity Error status bit when it detects the following error conditions:
  1. The Controller receives a poisoned completion from the link in response to a request.
  2. The Controller sends out a poisoned write request on the link (this may be because an underflow occurred during the packet transfer at the host interface of the Controller).
When this bit is 0, the Master Data Parity Error status bit is never set. This field can be written from the local management bus.
 0x0
7 R Reserved [R1] Reserved 0x0
8 R/W SERR Enable [SE] Enables the reporting of fatal and non-fatal errors detected by the Controller to the Root Complex. This field can be written from the local management bus. 0x0
9 R Reserved [R2] Reserved 0x0
10 R/W INTx Message Disabled [IMD] Enables or disables the transmission of INTx Assert and De-assert messages from the Controller. Setting this bit to 1 disables generation of INTx assert/de-assert messages in the Controller. This field can be written from the local management bus. 0x0
15:11 R Reserved [R3] Reserved 0x0
18:16 R Reserved [R4] Reserved 0x0
19 R Interrupt Status [IS] This bit is valid only when the Controller is configured to support legacy interrupts. Indicates that the Controller has a pending interrupt, that is, the Controller has sent an Assert_INTx message but has not transmitted a corresponding Deassert_INTx message. 0x0
20 R Capabilities List [CL] Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1. 0x1
23:21 R Reserved [R5] Reserved 0x0
24 R/WOCLR Master Data Parity Error [MDPE]
When the Parity Error Response enable bit is 1, the Controller sets this bit when it detects the following error conditions:
  1. The Controller receives a poisoned completion from the link in response to a request.
  2. The Controller sends out a poisoned write request on the link (this may be because an underflow occurred during the packet transfer at the host interface of the Controller).
This bit remains 0 when the Parity Error Response enable bit is 0. This field can also be cleared from the local management bus by writing a 1 into this bit position.
 0x0
26:25 R Reserved [R6] Reserved 0x0
27 R/WOCLR Signaled Target Abort [STA] This bit is set when the Controller has sent a completion to the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. 0x0
28 R/WOCLR Received Target Abort [RTA] This bit is set when the Controller has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management bus by writing a 1 into this bit position. 0x0
29 R/WOCLR Received Master Abort [RMA] This bit is set when the Controller has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management bus by writing a 1 into this bit position. 0x0
30 R/WOCLR Signaled System Error [SSE] If the SERR enable bit is 1, this bit is set when the Controller has sent out a fatal or non-fatal error message on the link to the Root Complex. If the SERR enable bit is 0, this bit remains 0. This field can also be cleared from the local management bus by writing a 1 into this bit position. 0x0
31 R/WOCLR Detected Parity Error [DPE] This bit is set when the Controller has received a poisoned TLP. The Parity Error Response enable bit (bit 6) has no effect on the setting of this bit. This field can also be cleared from the local management bus by writing a 1 into this bit position. 0x0