Base Address Register 0 @0x10
This is one of the six Base Address Registers defined by the PCI Specifications 3.0. These
registers are used to define address ranges for memory and I/O access to the Endpoint device.
During the initial configuration of the device, the configuration program determines the size
of the address range defined by the BAR by writing a pattern of all 1s into the BAR, reading
back from the BAR, and noting the position of the first 1 (the most significant) in the
returned value. A value of 0 is returned by the Controller if BAR 0 is not configured.
Otherwise, the number of 1s returned is based on the size of the BAR. BAR 0 can be setup as
32-bit memory or I/O BAR, or can be paired with BAR 1 to form a 64-bit memory BAR. The
settings of this BAR are defined in the BAR Configuration Register associated with this PF. The
BAR aperture can be controller in two different ways:
- When the Resizable BAR Capability is enabled, the aperture is controlled by the setting of the BAR width field in Resizable BAR Control Register. The Resizable BAR Capability is enabled by setting the Enable Resizable BAR Capability bit (bit 31) of the associated Physical Function BAR Configuration Register 1.
- When the Resizable BAR Capability is disabled for the Physical Function, the aperture is controlled by the setting of the PF BAR Configuration Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R | Memory Space Indicator [MSI0] | Specifies whether this BAR defines a memory address range or an I/O address range (0 = memory, 1 = I/O). The value read in this field is determined by the setting of BAR Configuration Registers of the associated Physical Function. | 0x0 |
| 1 | R | Reserved [R7] | This bit is hardwired to 0 for both memory and I/O BARs. | 0x0 |
| 2 | R | Size [S0] |
When the BAR is used to define a memory address range, this
field indicates whether the address range is 32-bit or 64-bit (0 =
32-bit, 1 = 64 bit).
For 64-bit address ranges, the value in BAR 1 is treated as a
continuation of the base address in BAR 0. The value read in this
field is determined by the setting of BAR Configuration Registers
of the associated Physical Function.
|
0x0 |
| 3 | R | Prefetchability [P0] |
When the BAR is used to define a memory address range, this
field declares whether data from the address range is prefetchable
(0 = non- prefetchable, 1 = prefetchable). The value read in this
field is determined by the setting of BAR
Configuration Registers of the associated Physical Function.
|
0x0 |
| 7:4 | R | Reserved [R8] | These bits are hardwired to 0. | 0x0 |
| 11:8 | R |
Base Address
- RO part [BAMR0]
|
This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated Physical Function. All other bits are not writeable, and are read as 0's. | 0x0 |
| 31:12 | R/W |
Base Address
- RW part [BAMRW]
|
This field defines the base address of the memory address range. The number of implemented bits in this field determines the BAR aperture configured in BAR Configuration Registers of the associated Physical Function. | 0x0 |