Link Control3 Register @0x304
This register is part of the Secondary PCI Express Extended Capability Structure. It contains bits to control the link equalization procedure at 8 GT/s or 16 GT/s speed.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | Perform Equaliztion [PE] | The state of this bit determines whether the Controller performs link equalization when the link is retrained by the local software. If this bit is set to 1 when the local software sets the Link Retrain bit in the Link Control Register, and the target link speed is 8 GT/s or 16 GT/s, the LTSSM of the Controller will go through the link equalization states during the retraining. | 0x0 |
| 1 | R/W | Link Equalization Request Interrupt Enable [LERIE] | This bit enables the activation of the LOCAL_INTERRUPT_OUT output of the Controller when the Link Equalization Request bit in the Link Status 2 Register Or the Link Equalization Request 16.0 GT/s in the 16GTs Status Register is set. | 0x0 |
| 8:2 | R | Reserved [R1] | Reserved | 0x0 |
| 12:9 | R/W | Enable Lower SKP OS Generation Vector [ELSOSGV] | When the Link is in L0 and the bit in this field corresponding to the current Link speed is Set, SKP Ordered Sets are scheduled at the rate defined for SRNS, overriding the rate required based on the clock tolerance architecture. | 0x0 |
| 31:13 | R | Reserved [R2] | Reserved | 0x0 |