LTSSM Transition Debug Control Register01 @0xf90

This register enables firmware to program two specific LTSSM state transitions to be detected and optionally paused for firmware control.

Table 1. i_ltssm_transition_debug_ctrl_reg01
Bits SW Name Description Reset
0 R/W LTSSM State Transition 0 Freeze Enable [LST0FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 0 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 0. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 0. LTSSM will continue to next legal state.
 0x0
1 R/W LTSSM State Transition 0 Check Enable [LST0CHEN] This bit enables the LTSSM transition 0 check.
  • 1: LTSSM State transition 0 check is enabled.
  • 0: LTSSM State transition 0 check is disabled.
 0x0
8:2 R/W Current LTSSM State 0 [CLTST0] This is the 7-bit Current LTSSM State of LTSSM transition 0 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
15:9 R/W Previous LTSSM State 0 [PLTST0] This is the 7-bit Previous LTSSM State of LTSSM transition 0 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
16 R/W LTSSM State Transition 1 Freeze Enable [LST1FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 1 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 1. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 1. LTSSM will continue to next legal state.
 0x0
17 R/W LTSSM State Transition 1 Check Enable [LST1CHEN] This bit enables the LTSSM transition 1 check.
  • 1: LTSSM State transition 1 check is enabled.
  • 0: LTSSM State transition 1 check is disabled.
 0x0
24:18 R/W Current LTSSM State 1 [CLTST1] This is the 7-bit Current LTSSM State of LTSSM transition1 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
31:25 R/W Previous LTSSM State 1 [PLTST1] This is the 7-bit Previous LTSSM State of LTSSM transition1 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0