MSI Pending Bits Register @0xa4

This register contains the MSI pending interrupt bits, one for each of the interrupt levels. This field can be written from the local management APBbus.

Table 1. i_msi_pending_bits

Bits	SW	Name	Description	Reset
0	R	MSI Pending Bits [MP]	Pending bits for MSI interrupts. This register contains the MSI pending interrupt bits, one for each of the interrupt levels. This field can be written from the local management APBbus. The Multiple Message Capable field of the MSI Control Register specifies the number of distinct interrupts for the Function, which determines the number of valid pending bits. Please note that if the Multiple Message Capable field is changed from the local management APBbus then the width of the MSI Pending Bits field also changes accordingly.	0x0
31:1	R	Reserved [R0]	Please note that if the Multiple Message Capable field is changed from the local management APBbus then the width of this field also changes accordingly.	0x0