Command and Status Register @0x4

16-bit Command Register and 16-bit Status Register.

Table 1. i_command_status
Bits SW Name Description Reset
0 R/W I/O-Space Enable [ISE] For a Function with a Type 1 Configuration Space header (Controller in RP Mode), this bit controls the response to I/O Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit.

Client must check that this bit is set to '1' before initiating any I/O requests on the pcie_master_AXI interface.

 0x0
1 R/W Mem-Space Enable [MSE] For a Function with a Type 1 Configuration Space header (Controller in RP Mode), this bit controls the response to Memory Space accesses received on its Primary Side. Note: The Controller does not generate any response based on this bit.

Client must check that this bit is set to '1' before initiating any Memory requests on the pcie_master_AXI interface.

0x0
2 R/W Bus-Master Enable [BE] For a Function with a Type 1 Configurations Space header (Controller in RP Mode), this bit controls forwarding of Memory or I/O Requests by a Port in the Upstream direction. Note: The Controller does not generate any response based on this bit.
Client application logic must use this bit and respond to requests appropriately:
  • When this bit is '1', Client logic can process the Memory and I/O Requests received from PCIe Link normally.
  • When this bit is '0', Client logic must handle Memory and I/O Requests received from PCIe Link as Unsupported Requests.
 0x0
5:3 R Reserved [R0] Reserved 0x0
6 R/W Parity Error Response Enable [PERE] When this bit is 1, the Controller sets the Master Data Parity Error status bit when it detects the following error conditions:
  1. The Controller receives a poisoned completion from the link in response to a request.
  2. The Controller sends out a poisoned write request on the link (this may be because an underflow occurred during the packet transfer at the host interface of the Controller).
When this bit is 0, the Master Data Parity Error status bit is never set.		 0x0
7 R Reserved [R1] Reserved 0x0
8 R/W SERR Enable [SE] Enables the reporting of fatal and non-fatal errors detected by the Controller to the Root Complex. 0x0
9 R Reserved [R2] Reserved 0x0
10 R/W INTx Message Disabled [IMD] Enables or disables the transmission of INTx Assert and De-assert messages from the Controller. The setting of this bit has no effect on the operation of the Controller in the RC mode. 0x0
15:11 R Reserved [R3] Reserved 0x0
18:16 R Reserved [R4] Reserved 0x0
19 R Interrupt Status [IS] This bit is valid only when the Controller is configured to support legacy interrupts. Indicates that the Controller has a pending interrupt; that is, the Controller has sent an Assert_INTx message but has not transmitted a corresponding Deassert_INTx message. 0x0
20 R Capabilities List [CL] Indicates the presence of PCI Extended Capabilities registers. This bit is hardwired to 1. 0x1
23:21 R Reserved [R5] Reserved 0x0
24 R/WOCLR Master Data Parity Error [MDPE] When the Parity Error Response enable bit is 1, the Controller sets this bit when it detects the following error conditions:
  1. The Controller receives a poisoned request from the link.
  2. The Controller has sent a Poisoned Completion downstream to the link This bit remains 0 when the Parity Error Response enable bit is 0.
This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.		 0x0
26:25 R Reserved [R6] Reserved 0x0
27 R/WOCLR Signaled Target Abort [STA] This bit is set when the Controller has sent a completion to the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
28 R/WOCLR Received Target Abort [RTA] This bit is set when the Controller has received a completion from the link with the Completer Abort status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
29 R/WOCLR Received Master Abort [RMA] This bit is set when the Controller has received a completion from the link with the Unsupported Request status. This field can also be cleared from the local management APB bus by writing a 1 into this bit position This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
30 R/WOCLR Signaled System Error [SSE] The Controller sets this bit:
  • On receiving an error message from the link, if SERR-Enable in PCI Command Register is 1 and SERR-Enable in the Bridge Control Register is also 1.
  • On any internal Fatal/Non-Fatal error detected, if SERR-Enable in PCI Command Register is 1.
This field can also be cleared from the local management APB bus by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.		 0x0
31 R/WOCLR Detected Parity Error [DPE] This bit is set when the Controller has received a poisoned TLP. The Parity Error Response enable bit (bit 6) has no effect on the setting of this bit. This field can also be cleared from the local management bus APB by writing a 1 into this bit position. This field can be forced to 1 from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0