Lane Margining at Receiver Error Status 2 Register @0xce0
The Lane Margining at Receiver PHY Error Status fields are implemented in this Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Invalid PHY Margining Command [IPHYMC] | When the Controller receives an Invalid Margining Command from PHY over PIPE Interface, the 8-bit PIPE command is logged in this register for debug. Only the first Error is logged in thisregister. This field is valid only when Bit-5, Invalid PHY Margining Command Received, of the i_local_error_status_2_register is set. Bit-5 of the i_local_error_status_2_register has to be cleared by local firmware before another error can be logged in this field. . | 0x0 |
| 11:8 | R | Invalid PHY Margining Command Lane Number [IPHYMCLN] | This field reports the Lane Number for which the Invalid command was received. 0000: Lane 0.0001: Lane 1. and so on. This field is valid only when Bit-5, Invalid PHY Margining Command Received, of the i_local_error_status_2_register is set. Bit-5 of the i_local_error_status_2_register has to be cleared by local firmware before another error can be logged in this field. . | 0x0 |
| 13:12 | R | Reserved [RES12] | Reserved | 0x0 |
| 17:14 | R | Write Ack Wait Timeout Lane Number [WAWTLN] | This field reports the Lane Number for which the Controller detected a 10ms timeout. 0000: Lane 0. 0001: Lane 1. and so on. This field is valid only when Bit-6, Write Ack Wait Timeout Error, of the i_local_error_status_2_register is set. Bit-6 of the i_local_error_status_2_register has to be cleared by local firmware before another error can be logged in this field. . | 0x0 |
| 21:18 | R | Unexpected PHY Response Lane Number [UPRLN] | This field reports the Lane Number for which the Controller received an unexpected PHY Response for Lane Margining. Unexpected PHY Response is detected by Controller if PHY writes to the Margin Status or the Margin NAK bits of RX Margin Status 0 Register when no change in Start Margin or Margin Offset issued by Controller or after the Write Ack Wait Timeout. 0000: Lane 0. 0001: Lane 1. and so on. This field is valid only when Bit-7, Unexpected PHY Response Received, of the i_local_error_status_2_register is set. Bit-7 of the i_local_error_status_2_register has to be cleared by local firmware before another error can be logged in this field. . | 0x0 |
| 31:22 | R | Reserved [RES22] | Reserved | 0x0 |