Gen 4 Link Equalization Debug Register @0x3c4

This register is used to reflect the negotiated TX Preset, Coefficients at the end of GEN4 Link Equalization. When the Controller is an Endpoint, this register reflects the Preset/Coefficients applied to the Endpoint Transmitter at the end of Gen4 Equalization Phase 3. When the Controller is an RC, this register reflects the Preset/Coefficients applied to the RC Transmitter at the end of Gen4 Equalization Phase 2.

Table 1. i_gen4_link_eq_debug_status_reg_lane1

Bits	SW	Name	Description	Reset
3:0	R	Link Equalization TX Preset [LEQTXPR]	TX Preset agreed upon for this lane.	0x8