Linkwidth Control Register @0x50

This register can be used to re-train the link to a different width without bringing the link down. This register can also be used to re-train the link to a different speed without bringing the link down.

Table 1. i_linkwidth_control_reg
Bits SW Name Description Reset
3:0 R/W Target Lane Map [TLM] This field contains the bitmap of the lanes to be included in forming the link during the re-training.
  • 0001 - Retrain to a x1 link
  • 0011 - Retrain to ax2 link
  • 1111 - Retrain to a x4 link
If the target lane map includes lanes that were inactive when re-training is initiated, then both the Controller and its link partner must support the LinkWidth Upconfigure Capability to be able to activate those lanes. In RC Mode, the user can check if the remote node has this capability by reading the Remote Link Upconfigure Capability Status bit in Physical Layer Configuration Register 0 after the link first came up.		 4'b1111
15:4 R Reserved [R0] Reserved 0x0
16 R/W Link Upconfigure Retrain Link [RL] Writing a 1 into this field results in the Controller re-training the link to change its width. When setting this bit to 1, the software must also set the target lane-map field to indicate the lanes it desires to be part of the link. The Controller will attempt to form a link with this set of lanes. The link formed at the end of the retraining may include all of these lanes (if both nodes agree on them during re-training), or the largest subset that both sides were able to activate. This bit is cleared by the internal logic of the Controller after the re-training has been completed and link has reached the L0 state. Software must wait for the bit to be clear before setting it again to change the link width.

NOTE: LINK WIDTH CHANGE FEATURE IS BEING DEPRECATED. FOR POWER SAVING, IT IS RECOMMENDED TO USE L1.

 0x0
17 R/W Disable Auto Gen2 Speed Change [DSAG2SC] This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen2 capability and if Gen2 is the highest common supported speed the Controller (RP) autonomously initiates Gen1 to Gen2 speed change. If Gen2 autonomous speed change was unsuccessful, then the Link transitions back to Gen1 L0. Software can re-initiate Gen2 speed change. Autonomous Speed Change to Gen2 can be disabled by programming this bit to 1. 0x0
18 R/W Disable Auto Gen3 Speed Change [DSAG3SC] This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen3 capability, the Controller (RP) autonomously initiates Gen1 to Gen3 speed change, equalization. If Gen3 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen1 L0. Software can re-initiate Gen3 speed change. Autonomous Speed Change to Gen3 can be disabled by programming this bit to 1. 0x0
19 R/W Disable Auto Gen4 Speed Change [DSAG4SC] This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen4 capability and if Gen3 speed change, equalization was successful, the Controller (RP) autonomously initiates Gen3 to Gen4 speed change, equalization. If Gen4 autonomous speed change/equalization was unsuccessful, then the Link transitions back to Gen3 L0. Software can re-initiate Gen4 speed change. Autonomous Speed Change to Gen4 can be disabled by programming this bit to 1.

Note: IfDisable Auto Gen3 Speed Change is disabled, then Auto Gen4 Speed Change must also be disabled by setting this bit to 1.

 0x0
20 R/W Disable Auto Gen5 Speed Change [DSAG5SC] This bit is used Only in RP mode. This bit is not used in EP mode of the Controller. During initial link training, if both components advertise Gen5 capability and if Gen4 speed change, equalization was successful, the Controller (RP) autonomously initiates Gen4 to Gen5 speed change, equalization. If Gen5 autonomous speed change/equalization was unsuccessful, then the Link transitionsback to Gen4 L0. Software can re-initiate Gen5 speed change. Autonomous Speed Change to Gen5 can be disabled by programming this bit to 1.

Programming Note1: When either (No Eq Capable) Or (Equalization Bypass to Highest Rate)Support is advertised in pl_32gts_capabilities_reg, then the i_linkwidth_control_reg[20:17] must be (4'b0000) or (4'b1110) or (4'b1111).

Programming Note2: When both (No Eq Capable) and (Equalization Bypass to Highest Rate) Supportare Not advertised in pl_32gts_capabilities_reg, then the i_linkwidth_control_reg[20:17] must be (4'b0000) or (4'b1000) or (4'b1100) or (4'b1110) or (4'b1111).

 0x0
23:21 R Reserved [R21] Reserved 0x0
26:24 R/W EP Target Link Speed [EPTLS] This field contains the Link Speed that the EP intends to change to during the re-training. Client needs to ensure that this field is programmedto a speed which is lesser than or equal to the Target Link Speed field of PF0 Configuration Link Control 2 Register. Client also needs to ensure that this does not exceed PCIE_GENERATION_SEL strap input. Defined encodings of this field are:
  • 000 - GEN1
  • 001 - GEN2
  • 010 - GEN3
  • 011 - GEN4
  • 100 - Reserved
 0x0
30:27 R Reserved [R2] Reserved 0x0
31 R/W EP Link Speed Change Retrain Link [EPLSCRL] Writing a 1 into this field results in the Controller re-training the link to change its speed. When setting this bit to 1, the software must also setthe EP Target Link Speed field to indicate the speed that the EP desires to change on the link. The EP Controller will attempt to change the link to this speed. This bit is cleared by the internal logic of the Controller after the re-training has been completed and link has reached the L0 state. Software must wait for the bit to be clear before setting it again to change the link speed. 0x0