Power Management Capabilities Register @0x80
This location contains the Power Management Capabilities Register, its Capability ID, and a pointer to the next capability. This version of the Controller supports the PCI power states D0, D1, and D3.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Capability ID [CID] | Identifies that the capability structure is for Power Management. This field is set by default to 01 hex. It can be re-written independently for each Function from the local management bus. | 0x01 |
| 15:8 | R | Capabilities Pointer [CP] | Contains pointer to the next PCI Capability Structure. This field can be re-written independently for each Function from the local management bus. | 8'h90 |
| 18:16 | R | Version ID [VID] | Indicates the version of the PCI Bus Power Management Specifications that the Function implements. This field is set by default to 011 (Version 1.2). It can be re-written independently for each Function from the local management bus. | 0x3 |
| 19 | R | PME Clock [PC] | Not applicable to PCI Express. This bit is hardwired to 0. | 0x0 |
| 20 | R | Reserved [R0] | Reserved | 0x0 |
| 21 | R | Device Specific Initialization Bit [DSI] | This bit, when set, indicates that the device requires additional configuration steps beyond setting up its PCI configuration space to bring it to the D0 active state from the D0 uninitialized state. This bit is hardwired to 0. | 0x0 |
| 24:22 | R | Max Current Required from Aux Power Supply [MCRAPS] | Specifies the maximum current drawn by the device from the aux power source in the D3cold state. This field is not implemented in devices not supporting PME notification when in the D3cold state, and is therefore hardwired to 0. | 0x0 |
| 25 | R | D1 Support [D1S] | Set if the Function supports the D1 power state. This bit can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. | 0x1 |
| 26 | R | D2 Support [D2S] | Set if the Function supports the D2 power state. Currently hardwired to 0. | 0x0 |
| 27 | R | PME Support for D0 State [PSD0S] | Indicates whether the Function is capable of sending PME messages when in the D0 state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. | 0x01 |
| 28 | R | PME Support for D1 State [PSD1S] | Indicates whether the Function is capable of sending PME messages when in the D1 state. This bit can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. | 0x1 |
| 29 | R | PME Support for D2 State [PSD2S] | Indicates whether the Function is capable of sending PME messages when in the D2 state. This bit is hardwired to 0 because D2 state is not supported. | 0x0 |
| 30 | R | PME Support for D3(hot) Statue [PSDHS] | Indicates whether the Function is capable of sending PME messages when in the D3hot state. This bit is set to 1 by default, but can be modified from the local management bus by writing into Function 0. All other Functions assume the value set in Function 0s Power Management Capabilities Register. | 0x01 |
| 31 | R | PME Support for D3(cold) State [PSDCS] | Indicates whether the Function is capable of sending PME messages when in the D3cold state. Because the device does not have aux power, this bit is hardwired to 0. | 0x0 |