Region 5 Outbound AXI to PCIe Address Translation Register 0 @0xa0

Provides bits 31:8 of the PCIe address and the number of AXI address bits passed through.

Table 1. addr0

Bits	SW	Name	Description	Reset
5:0	R/W	Number_bits [5:0] [num_bits]	Number_bits + 1 bits are passed through from AXI address to the PCIe address.	6'h00
7:6	R	Reserved [rsvd]	Bits 7 and 6 are reserved.	2'b00
31:8	R/W	Address bits [31:8] [data]	Bits [31:8] of PCIe Address Register for region N.	24'h00000000