Low Power Debug and Control Register 1 @0xc8c

This register controls internal behavior of controller for low power operations. Adjustment of this register is not required for normal operations.

Table 1. low_power_debug_and_control1
Bits SW Name Description Reset
7:0 R L1 or L1.x Exit Trigger conditions [L1ER] This field shows the values of possible L1 or L1-substate exit triggers. This is useful for debug. This is captured during L1 or L1-substate exit process. This field is reset during L1 entry.
  • 0 : CLIENT_REQ_EXIT_L1 asserted;
  • 1 : Electrical Idle exit detected at link.
  • 2 : New TLP request detected.
  • 3 : Internal request to send TLP. This includes CFG completions, internal messages, and INTx messages.
  • 4 : Pending TX traffic available. This could be traffic from DMA and blocked traffic due to credits at AXI.
  • 5 : #CLKREQ assert detected.
  • 6 : CLIENT_REQ_EXIT_L1_SUBSTATE asserted
  • 7 : Reg Access request detected.
Triggers #5,6,7 are valid only with L1-substate supported configs.		 0x0
31:8 R RSVD RSVD 24'h000000