Debug Mux Control 3 Register @0x23c

Table 1. i_debug_mux_control_3_reg
Bits SW Name Description Reset
0 R Reserved [R0] Reserved 0x0
1 R/W Disable GEN4 data parity check [DGDPC] To disable GEN4 data parity check from LM register. 0x0
2 R/W Disable link training error [DLTE] Used to disable and enable link training error logging and by default it is enabled. 0x0
3 R/W Disable surprise down error status [DSDES] Used to disable and enable Surprise Down Error status logging and by default it is enabled. 0x0
4 R/W Disable Rcb check [DRC] USed to disable and enable the RCB checker and by default it is disable (wrire 0 to enable and write 1 to disable). 1'b1
7:5 R Reserved [R5] Reserved 0x0
9:8 R/W Config LW Eval Window [CLWEW] This field can be used to control the window in which the Controller waits during Configuration states to determine link width. After two consecutive TS1s are received on any lane, the Controller waits for the time defined in this window for other lanes to receive TS1s before determining link width.
  • 00: Wait for 4 TS1 window
  • 01: Wait for 8 TS1 window
  • 10: Wait for 16 TS1 window
  • 11: Wait for 24 TS1 window
2'b00
10 R/W Disable LTSSM Freeze 1US Recovery Equalization Phase0 [DLF1USEQ] As per PCIe specification, the EP is permitted to wait for up to 500 ns after entering Phase 0 before evaluating received information for TS1 Ordered Sets if it needs the time to stabilize its Receiver logic. Similarly, the RP is permitted to wait for up to 500 ns after entering Phase 1 before evaluating received information for TS1 Ordered Sets if it needs the time to stabilize its Receiver logic. Controller implements a 1 μs time on entering Recovery Equalization Phase0/Phase1 during which the received TS1 is ignored. Writing a 1 disables the 1 μs wait. 1'b1
11 R/W Disable Support for all Ranges (A,B,C,D in Completion Timeout) [DSRCT] As per PCIe specification, the completion timeout values for the outbound request must be in) Ranges (A,B,C,D) as per the given timeout values. Within these ranges there are Subrange (0 or 1) given which will determine the actual completion timeout values to be used. Disable this bit to support only 1 range (Range B). 1'b1
12 R/W Error Emulation feature enable for AER registers. [EEFER] When this bit is set, the AER Uncorrectable/Correctable Error Status registers can be written through LM registers. 1'b0
13 R/W Error Emulation feature enable for Fatal ErrorInterrupt. [EEFEFE] This bit is pulse signal which triggers Fatal error Interrupt. 1'b0
14 R/W Error Emulation feature enable for Non-Fatal Error Interrupt. [EEFENFE] This bit is pulse signal which triggers Non-Fatal error Interrupt. 1'b0
15 R/W Error Emulation feature enable for Correctable Error Interrupt. [EEFECE] This bit is pulse signal which triggers Correctable error Interrupt. 1'b0
17:16 R Reserved [R16] Reserved 0x0
18 R/W Disable Config.Idle to Recovery after Timeout [DCIRTO] This bit controls the LTSSM transition from Config.Idle to Recovery transition if 2 ms timeout occured in Config.Complete state.
  • 0: Transition from Config.Idle to Recovery if 2 ms timeout occured in Config.Complete state.
  • 1: Transition from Config.Idle to L0 transition if IDLE symbols received regardless of 2 ms timeout occuredin Config.Complete state. This bit must be at default value of 0 to be compliant to PCIe spec for Config.Idle state.
 1'b0
19 R/W Disable Link Number Transmit on Discontinuous Lanes [DLNTDL] This bit controls the Link Number Transmit in Configuration.LinkWidth.Start state in EP Mode when one or more lane is disconnected.
  • 0: Transmit the received non-PAD LinkNum on all lanes that receive non-PAD LinkNum in Config.LW.Start state.
  • 1: Transmit the received non-PAD LinkNum on a contiguous set of lanes that receive non-PAD LinkNum in Config.LW.Start state. This bit must be atdefault value of 0 to be compliant to PCIe spec for Config.LW.Start state.
 1'b0
20 R/W Disable Loopback Entry TS1 Loopback bit check [DLETS1LC] This bit controls the TS1 check during Loopback.Entry to Loopback.Active transition in Loopback Slave mode. In Loopback.Entry state, Next state is Loopback.Active if the data rate is 8.0 GT/s or higher and two consecutive TS1 Ordered Sets are received on all active Lanes.
  • 0: Transition if two consecutive TS1 receieved on all active lanes with Loopback bit set.
  • 1: Transition if two consecutive TS1 receieved on all active lanes without checking Loopback bit. This bit must be at default value of 1 to be compliant to PCIe spec for Loopback.Entry state.
 1'b1
21 R/W Disable to clear nak_schedule before TLP end [DCNSBTE] When set NAK_SCHEDULE flag can be cleared before the TLP end else NAK_SCHEDULE flag will be clear at end of TLP PKT. 1'b0
22 R/W Disable EIOS Consecutive Counter Reset Unexpected Data [DECCRUD] This bit controls the EIOS Consecutive Counter.
  • 0: Reset EIOS consecutive counter if unexpected data received in between EIOS.
  • 1: Hold EIOS consecutive counter if unexpected data received after receiving 1 EIOS OS.
 1'b0
23 R/W Disable rx elec idle exit in any check polling complaince [DREIECPC]
  • 0: Check for electrical idle exit in ANY active lane for exit from Polling.Complaince at Gen1.
  • 1: Check for electrical idle exit in ALL active lanes for exit from Polling.Complaince at Gen1.
Note: This register must be 0 to be compliant with the PCIe Spec.

Note: This register is used only when PCIE_GENERATION_SEL==0. When PCIE_GENERATION_SEL> 0, Controller exits Polling.Complaince state based on ANY active lane as per PCIe specification.

 1'b0
24 R/W Disable Link Number check in configuration lanenumwait ltssm state [DLNCCL] As per PCIe specification, in Configuration.Lanenum.Wait state, a device must check if any of the Lanes receive two consecutive TS1 Ordered Sets that have a Lane number different from when the Lane first entered Configuration.Lanenum.Wait, and not all the Lanes Link numbers are set to PAD Controller implements this check in Controller.Lanenum.Wait state. The received Link Number can be either PAD or non-PAD.
  • 0: Check for PAD/non-PAD Linknum in received TS1sin Configuration.Lanenum.Wait state.
  • 1: Check for only non-PAD Linknum in received TS1s in Configuration.Lanenum.Wait state.
Note: This register must be 0 to be compliant with the PCIe Spec.		 1'b0
25 R/W Disable EIOS detection in gen2 polling complaince [DEIOSGPC] When Polling.Compliance is entered due to Enter Compliance bit set, the exit is based on received EIOS or Enter Compliance bit programmed back to 0. This bit is used to control EIOS check in Polling.Compliance state.
  • 0: Enable EIOS-idle sequence detect logic in gen2 Polling.Compliance.
  • 1: Disable EIOS-idle sequence detect logic in gen2 Polling.Complaince.
Note: This register must be 0 to be compliant with the PCIe Spec.		 1'b0
26 R/W Disable TS1 Coefficient Mismatch Check Hold [DTSCMCH]
  • 0: Register and Hold the coefficient mismatch and use during Recovery.Rcvr.Lock -> Recovery.Rcvr.Cfg transition.
  • 1: Do not register. Check coefficient mimatch only during Recovery.Rcvr.Lock -> Recovery.Rcvr.Cfg transition.
Note: This register must be 0 to be compliant with the PCIe Spec.		 1'b0
27 R/W Disable lane equalization control register reset after hot reset [DLERHR]
  • 0: Reset Lane Equalization Control Register, PL_16GTS Lane Equalization Control Register during Link Down/Hot Reset.
  • 1: Do not reset Lane Equalization Control Register, PL_16GTS Lane Equalization Control Register during Link Down/ Hot Reset.
Note: This register must be 0 to be compliant with the PCIe Spec.		 1'b0
28 R/W Disable to send a NAK due to phy error [DSNPE] When set Data Link Layer will not send a NAK when PL indicated Phy Error for a received TLP else Nak will be schedule for phy error. 1'b0
29 R/W Disable zero bus dev num for UR config compl [DZBDFURC] When set Controller will copy the Bus and Device numbers from the Config Read into the completion for Config Reads done prior to any Config Write (Bus Device Number Capture not done). 1'b0
30 R/W Disable Receive SKP ENDError Check [DRSEC] As per PCIe specification, when using 128b/130b encoding, a received SKP Ordered set can be eight, 12, 16, 20, or 24 Symbols. The Elastic Buffer in the PHY can also add four symbols to the received SKP OS. The SKP OS bypasses Scrambling and Descrambling. While processing the received SKP OS, the Descrambler has two modes selected by this bit:
  • 0: stop SKP OS processing after SKP_ENDis received.
  • 1: stop SKP OS processing after SKP_END or 28 symbols received.
 1'b0
31 R/W Disable Current Link Speed Update in Recovery.Speed State [DCLSRSS] As per PCIe specification, during speed change in Recovery.Speed state, the new data rate must be reflected in the Current Link Speed field of the Link Status Register. This bit can be used to control the update of Current Link Speed status register:
  • 0: Update Current Link Speed status register in Recovery.Speed LTSSM state.
  • 1: Update Current Link Speed status register in L0 LTSSM state.
 1'b0