Prefetchable Memory Base,Prefetchable Memory Limit @0x24

This location contains the Prefetchable Memory Base Register and the Prefetchable Memory Limit Register. This register is enabled by programming the Root Complex BAR configuration register in the Local Management space.

Table 1. i_pcie_prefetch_base_limit

Bits	SW	Name	Description	Reset
15:0	R	Prefetchable Memory Base Register [PMBR]	This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.	16'h0
31:16	R	Prefetchable Memory Limit Register [PMLR]	This field can be read and written from the local management APB bus if prefetchable memory is enabled in the Root Complex BAR configuration register, else it is hardwired to zero. Its value is not used within the Controller.	16'h0