Gen 3 Gen 4 Link Equalization Control Register @0x37c

This register is used to Control GEN3, GEN4 Link Equalization Procedure.

Table 1. i_gen3_gen4_link_eq_ctrl_reg
Bits SW Name Description Reset
2:0 R/W Max Eval Convergence Count [MXECC] Controls the number of consecutive RxEqEval iterations with direction change feedback of 00s before Equalization Convergence is inferred.
  • 0 : Infer Convergence after 1 feedback of 000000
  • 1 : Infer Convergence after 2 feedback of 000000
  • 2 : Infer Convergence after 3 consecutive feedback of 000000.
  • 7 : Infer Convergence after 8 consecutive feedback of 000000.
Note: Each lane independently counts consecutive feedback of 000000.

Note: Count is reset after a non-000000 feedback on each lane.

0x0
3 R/W Disable Max Eval Iteration [DMEI] The MAX_EVAL_ITERATION input controls the maximum number of iterations in Equalization Phase2 (EP) or Phase3 (RP). This bit can be used to mask the MAX_EVAL_ITERATION and perform more iterations till Convergence or a 24ms timeout. 0x0
4 R/W EP 8GTs Request Equalization Retrain Link [EP8GRE] This bit can be used by Endpoint Device FW to request for 8GT/s Equalization redo. This bit can be set at any time after the Link is Up. Writing a 1 into this field results in the Controller to transition to Recovery. The Request Equalization bit in TS2 Ordered Sets will be set to 1 in Recovery.Rcvr.Cfg to request equalization at 8GTs. This bit is auto-cleared by the internal logic of the Controller after the re-training has been completed and link has reached the L0 state. This bit is also auto-cleared when not in Gen3 or Gen4. Device Firmware must wait for the bit to be clear before any subsequent retrain requests. 0x0
5 R/W EP 16GTs Request Equalization Retrain Link [EP16GRE] Writing a 1 into this field results in the Controller to transition to Recovery. The Request Equalization bit and Equalization Request Data Rate bit in TS2 Ordered Sets will be set to 1 in Recovery.Rcvr.Cfg to request equalization at 16GTs. This bit is auto-cleared by the internal logic of the Controller after the re-training has been completed and link has reached the L0 state. This bit is also auto-cleared when not in Gen3 or Gen4. Device Firmware must wait for the bit to be clear before any subsequent requests. 0x0
6 R Reserved [RES6] Reserved 0x0
7 R Reserved [RES7] Reserved 0x0
8 R/W Quiesce Guarantee 8GTs [QG8GT] This bit can be used to program the Quiesce Guarantee bit of the TS2 in Recovery.Rcvr.Cfg state during 8GT/s Request Equalization. 0x0
9 R/W Quiesce Guarantee 16GTs [QG16GT] This bit can be used to program the Quiesce Guarantee bit of the TS2 in Recovery.Rcvr.Cfg state during 16GT/s Request Equalization. 0x0
10 R Reserved [RES10] Reserved 0x0
11 R Reserved [RES11] Reserved 0x0
15:12 R/W Max 8GTs Equalization Request Limit [MX8GERL] This register is used during error scenario where the coefficients at the end of Equalization mismatch with the coefficients agreed during Equalization. If Recovery.RcvrLock was entered from Recovery.Equalization, the Upstream Port must evaluate the equalization coefficients or preset received by all Lanes that receive eight TS1 Ordered Sets and note whether they are different from the final set of coefficients or preset that was accepted in Phase 2 of the equalization process.

Note: Mismatches are reported in Recovery.RcvrCfg by setting the Request Equalization bit of TS2 Ordered Sets. The number of 8GT/s Equalization Requests must be finite as per PCIe specification. This register can be used to program the maximum numberof 8GT/s equalization requests automatically initiated by the Endpoint.

  • 0000: Automatic 8GT/s Equalization Request Disabled.
  • 0001: Automatic 8GT/s Equalization request limit is 1.
  • 0010: Automatic 8GT/s Equalization request limit is 2.
  • 1111: Automatic 8GT/s Equalization requestlimit is 15.
 0x0
19:16 R/W Max 16GTs Equalization Request Limit [MX16GERL] This register is used during error scenario where the coefficients at the end of Equalization mismatch with the coefficients agreed during Equalization. If Recovery.RcvrLock was entered from Recovery.Equalization, the Upstream Port must evaluate the equalization coefficients or preset received by all Lanes that receive eight TS1 Ordered Sets and note whether they are different from the final set of coefficients or preset that was accepted in Phase 2 of the equalization process.

Note: Mismatches are reported in Recovery.RcvrCfg by setting theRequest Equalization bit of TS2 Ordered Sets. The number of 16GT/s Equalization Requests must be finite as per PCIe specification. This register can be used to program the maximum number of 16GT/s equalization requests automaticallyinitiated by the Endpoint.

  • 0000: Automatic 16GT/s Equalization Request Disabled.
  • 0001: Automatic 16GT/s Equalization request limit is 1.
  • 0010: Automatic 16GT/s Equalization request limit is 2.
  • 1111: Automatic 16GT/s Equalization request limit is 15.
 0x0
23:20 R Reserved [RES20] Reserved 0x0
30:24 R Reserved [RES24] Reserved 0x0
31 R/W Enable Retry RXEQEVAL After Feedback Error [EREVFBER] When the Controller receives a direction change feedback from the PHY, the feedback is applied to the current coefficients and checked for errors. During Equalization Phase2(EP) or Phase3(RP), 1 iteration is defined as (Number of Preset Feedback) + (Number of pipe_rxeqeval assertions). This bit controls the device feedback in an iteration in case of direction change errors:
  • 0: If feedback is invalid, then the Controller, discards the feedback and does not assert PIPE_INVALIDREQUEST and does not retry PIPE_RXEQEVAL in same iteration. The coefficient settings is kept unchanged in the iteration. Retry PIPE_RXEQEVAL in next iteration.
  • 1: If feedback is invalid, then the Controller asserts PIPE_INVALIDREQUEST to PHY, discards the feedback and retries PIPE_RXEQEVAL in same iteration till a valid feedback is received.
 0x0