Data Link Layer Timer Configuration Register @0x8
This register defines the replay timeout values used by the DL receive and transmit sides of the link. It can be read or written via the local management APB bus.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 8:0 | R/W | Transmit-Side Replay Timeout Adjustment [TSRT] | Additional transmit-side replay timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal replay timer timeout value computed by the Controller based on the PCI Express Specifications. This enables the user to make minor adjustments to the spec-defined replay timer settings. Its value is in multiples of (2 Symbol Times). At Gen1 adjustment range = (+2040 ns to -2048 ns). At Gen2 adjustment range = (+1020 ns to -1024 ns). At Gen3 adjustment range = (+510 ns to -512 ns). | 0x0 |
| 15:9 | R | Reserved [R9] | Reserved | 0x0 |
| 24:16 | R/W | Receive-Side ACK-NAK Replay Timeout Adjustment [RSART] | Additional receive side ACK-NAK timer timeout interval. This 9-bit value is added as a signed 2's complement number to the internal ACK-NAK timer timeout value computed by the Controller based on the PCI Express Specifications. This enables the user to make minor adjustments to the spec-defined replay timer settings.Its value is in multiples of (2 Symbol Times). At Gen1 adjustment range = (+2040 ns to -2048 ns). At Gen2 adjustment range = (+1020 ns to -1024 ns). At Gen3 adjustment range = (+510 ns to -512 ns). | 0x0 |
| 31:25 | R | Reserved [R25] | Reserved | 0x0 |