Link Capabilities Register @0xcc
This register advertises the link-specific capabilities of the device incorporating the PCIe core. There are no writable bits at this location. A read to this address returns the Link Capability Register fields of Physical Function 0.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R | Maximum Link Speed [MLS] | Indicates the maximum speed supported by the link (2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s per lane). This field is hardwired to 0001 (2.5GT/s) when the strap input PCIE_GENERATION_SEL is set to 0, to 0010 (5 GT/s) when the strap is set to 1, to 0011 (8 GT/s) when the strap input is set to 10, and to 0100 (16 GT/s) when the strap input is set to 11. | 0x4 |
| 9:4 | R | Maximum Link Width [MLW] | Indicates the maximum number of lanes supported by the device. This field is hardwired based on the setting of the LANE_COUNT_IN strap input. | 6'd4 |
| 11:10 | R | Active State Power Management [ASPM] | Indicates the level of ASPM support provided by the device. This field can be re-written independently for each Function from the local management bus. When SRIS is enabled in local management register bit, L0s capability is not supported and is forced low. | 0x3 |
| 14:12 | R | L0S Exit Latency [L0SEL] | Specifies the time required for the device to transition from L0S to L0. This parameter is dependent on the Physical Layer implementation. It can be re-written independently for each Function from the local management bus. | 0x2 |
| 17:15 | R | L1 Exit Latency [L1EL] | Specifies the exit latency from L1 state. This parameter is dependent on the Physical Layer implementation. It can be re-written independently for each Function from the local management bus. | 0x3 |
| 18 | R | Clock Power Management [CPM] | Indicates that the device supports removal of referenc clocks. It can be re-written independently for each function from the local management bus. | 0x0 |
| 19 | R | Surprise Down Error Reporting Capability [SDERC] | Indicates the capability of the device to report a Surprise Down error condition. This bit is hardwired to 0 as this version of the core does not support the feature. | 0x0 |
| 20 | R | Data Link Layer Active Reporting Capability [DLLARC] | Set to 1 if the device is capable of reporting that the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 as this version of the core does not support the feature. | 0x0 |
| 21 | R | Link Bandwidth Notification Capability [LBNC] | A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. Reserved for Endpoint. | 0x0 |
| 22 | R | ASPM Optionality Compliance [AOC] | Setting this bit indicates that the device supports the ASPM Optionality feature. It can be turned off by writing a 0 to this bit position through the local management bus. | 0x1 |
| 23 | R | Reserved [R5] | Reserved | 0x0 |
| 31:24 | R | Port Number [PN] | Specifies the port number assigned to the PCI Express link connected to this device. | 8'h0 |