Base Address Register 1 @0x14

This is one of the six Base Address Registers defined by the PCI Specifications 3.0. BAR 1 can be setup as 32-bit memory or I/O BAR, or can be paired with BAR 0 to form a 64-bit memory BAR. This register can be used in two distinct ways:

1. When BAR 0 defines a 64-bit memory address range, this register is used to define the high-order bits of the base address. The number of writable bits in this field is based on the aperture setting of the BAR.
2. When the BAR 0 is used to define a 32-bit memory address range or an I/O address range, this register can be used to define a new 32-bit memory address range or an I/O address range. The individual fields in the register have the same format as those of BAR 0 and is described below. The settings of this BAR are defined in the BAR Configuration Register associated with this PF. When configured as a 32-bit memory or I/O BAR, the BAR aperture can be controller in two different ways:
   1. When the Resizable BAR Capability is enabled, the aperture is controlled by the setting of the BAR width field in Resizable BAR Control Register 1. The Resizable BAR Capability is enabled by setting the Enable Resizable BAR Capability bit (bit 31) of the associated Physical Function BAR Configuration Register.
   2. When the Resizable BAR Capability is disabled for the Physical Function, the aperture is controlled by the setting of the Physical Function BAR Configuration Register.