Local Interrupt Mask Register @0x210
This register contains a mask bit for each interrupting condition. Setting the bit to 1 prevents the corresponding condition in the Local Error Status Register from activating the LOCAL_INTERRUPT output.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | PNP RX FIFOParity Error [PRFPE] | Parity error detected while reading from the PNP Receive FIFO RAM. | 1'b1 |
| 1 | R/W | Completion RX FIFO Parity Error [CRFPE] | Parity error detected while reading from the Completion Receive FIFO RAM. | 1'b1 |
| 2 | R/W | Replay RAM Parity Error [RRPE] | Parity error detected while reading from Replay Buffer RAM. | 1'b1 |
| 3 | R/W | PNP RX FIFOOverflow [PRFO] | Overflow occurred in the PNP Receive FIFO. | 1'b1 |
| 4 | R/W | Completion RX FIFO Overflow [CRFO] | Overflow occurred in the Completion Receive FIFO. | 1'b1 |
| 5 | R/W | Replay Timeout [RT] | Replay timer timed out. | 1'b1 |
| 6 | R/W | Replay Timer Rollover [RTR] | Replay timer rolled over after four transmissions of the same TLP. | 1'b1 |
| 7 | R/W | Phy Error [PE] | Phy error detected on receive side. | 1'b1 |
| 8 | R/W | Malformed TLP Received [MTR] | Malformed TLP received from the link. | 1'b1 |
| 9 | R/W | Unexpected Completion Received [UCR] | Unexpected Completion received from the link. | 1'b1 |
| 10 | R/W | Flow Control Error [FCE] | An error was observed in the flow control advertisements from the other side. | 1'b1 |
| 11 | R/W | Completion Timeout [CT] | A request timed out waiting for completion. | 1'b1 |
| 12 | R | Reserved [R12] | Reserved | 1'b0 |
| 16:13 | R | Reserved [R13] | Reserved | 0x0 |
| 17 | R/W | End to End Parity Error [EEPE] | The Controller detected an End-to-End Parity Error. | 1'b1 |
| 18 | R/W | Unmapped TC [UTC] | Unmapped TC error. | 0x1 |
| 19 | R/W | MSI Mask Value Change [MMVC] | MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller. | 0x1 |
| 20 | R | Reserved [R45] | Reserved | 1'b0 |
| 21 | R/W | Hardware Autonomous Width Change Disable Toggle [HAWCD] | This bit is used to mask interrupt that indicates that the Host toggled the Hardware Autonomous Width Change in the Endpoint Link Control Register through a Config Write. | 1'b1 |
| 22 | R | Reserved [R23_1] | Reserved | 0x0 |
| 24:23 | R | Reserved [R24] | Reserved | 0x0 |
| 25 | R/W | MSIX Function Mask Change [MSIXMSK] | This bit is used to mask interrupt that indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW. | 1'b1 |
| 27:26 | R | Reserved [R27] | Reserved | 0x0 |
| 28 | R | Reserved [R28] | Reserved | 0x0 |
| 29 | R/W | AXI master read FIFO RAM ECC uncorrectable error mask [AXIMASTER_RFIFO_ER_UN] | Mask for uncorrectbale axi master write FIFI RAM parity/ECC error. | 0x0 |
| 30 | R/W | AXI slave write FIFO RAM ECC uncorrectable error mask [AXISLAVE_WFIFO_ER_UN] | Mask for uncorrectbale AXI slave write FIFO RAM parity/ECC error. | 0x0 |
| 31 | R/W | AXI slave reorder RAM ECC uncorrectable error mask [REORDER_ER_UN] | Mask for uncorrectbale AXI slave reorder RAM parity/ECC error. | 0x0 |