Debug Mux Control 2 Register @0x234

Table 1. i_debug_mux_control_2_reg
Bits SW Name Description Reset
0 R/W Disable LOCALLF, LOCALFSsampling after speed change [DLFFS] As per PIPE 4.2 specification, the LOCALLF, LOCALFS outputs from PHY can be sampled uponf PHYSTATUS pulse after Reset# OR upon the first PHYSTATUS pulse after speed change to GEN3. This bit can be set to 1 to disable sampling after speed change to GEN3 or higher 0x0
1 R/W Enable Extended Config Snoop Read [EXTSNP] This bit can be set if extra clock cycles (up to 16) are required by the Client Application logic to respond with the Read Data on Configuration Snoop Interface. Please refer to the user guide section on Configuration Snoop Interface for timing diagrams. 0x0
2 R/W Disable SDS OS Check [DISSDSCHK] As per PCIe specification, When using 128b/130b encoding, next state is L0 if eight consecutive Symbol Times of Idle data are received on all configured Lanes. The Controller checks to ensure that the Idle symbols of data are received in Data Blocks after SDS OS. This check is enabled by default. Setting this bit to 1 turns off this check.This bit is recommended to be kept at the default value of 0. 0x0
3 R/W Enable Link Lane Number Check for Loopback and Link Disable [ENLNCHK] As per PCIe specification, LTSSM should transition to Disabled after any Lanes that are transmitting TS1 Ordered Sets receive two consecutive TS1 Ordered Sets with the Disable Link bit asserted. Similarly, LTSSM should transition to Loopback after all Lanes that are transmitting TS1 Ordered Sets, that are also receiving TS1 Ordered Sets, receive the Loopback bit asserted in two consecutive TS1 Ordered Sets. Controller ignores the Link and Lane Number in the Received TS1s with Loopback/Disable bit set. Setting this bit to 1 turns on the check for link number (assigned by RC in Recovery.Idle) and lane number (PAD in Config.LW.Start or as assigned by RC in Recovery.Idle). This bit is recommended to be kept at the default value of 0. 0x0
4 R/W ARI Capable Hierarchy Mode [ARICAPMOD] As per SR IOC specification, ARI Capable Hierarchy bit is only present in the lowest numbered PF of a Device. The Controller has two modes to determine the lowest numbered PF.
  • 0: The first PF which is enabled (PF0) is taken as the lowest numbered PF.
  • 1: The first PF which has a non-zero TOTAL_VF_COUNT field is taken as the lowest numbered PF(Default Mode).
 0x1
5 R/W Gen3 Block Alignment Check Disable [BLKALNCHK] When in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY. If the block alignment is lost, then the PHY may deassert pipe_rx_valid. Block Alignment may be lost if the received sync header is invalid. Controller supports detecting loss of block alignment while in a data stream in Gen3.
  • 0: Enable check for loss of Gen3 Block Alignment during data stream.
  • 1: Disable check for loss of Gen3 Block Alignment.
 0x0
7:6 R/W Gen3 Block Alignment Check Window [BLKALNWIN] When in the data stream at Gen3 or higher speeds, the pipe_rx_valid is asserted by the PHY. If the block alignment is lost, then the PHY may deassert pipe_rx_valid. Controller reports loss of block alignment if pipe_rx_valid or pipe_rx_data_valid=0 for a period consecutive clock cycles as programmed in this field.
  • 00: 8CORE_CLK cycles
  • 01: 16 CORE_CLK cycles
  • 10: 64 CORE_CLK cycles
  • 11: 256 CORE_CLK cycles
 0x1
8 R/W Gen4 Enable Spec Rev0.5 Features [ENG4REV05] When operating in Gen4 16GT/s, this Enables Gen4 Spec Revision 0.5 EIEOS and SKP features. When disabled, the Gen4 1.0 features are enabled, by default this bit is ZERO.
  • 1: Enable Gen4 0.5 Features
  • 0: Disable Gen4 0.5 Features (This enabled the Gen4 1.0 Features).
 0x0
9 R/W MSI Pending Status In Mode Select [MSIPIMS] If the Client wishes to use the MSI_PENDING_STATUS_IN Signal to Update the MSI pending Bits register, this bit needs to be set to 1. Otherwise the Pending Bits register is updated via the APB Interface 0x0
10 R/W Poisoned TLP Received Advisory Non-Fatal [PSNADV] As per PCIe specification 2.7.2.2, the following Poisoned TLP requests must be handled as Uncorrectable and not as Advisory: I/O Write Request, Memory Write Request, or non-vendor-defined Message with data that target a Control structure. Since it is not possible for the Controller to determine if the target is a Control or a non-Control strusture, the Controller implements this bit for the user to determine the required handling.
  • 1: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Advisory Non-Fatal Error.
  • 0: Poisoned TLP of type IOWr, MemWr, MsgD will be handled as Uncorrectable Error.
Note: Poisoned CplD will always be reported as Advisory Non-Fatal and is not controlled by this register setting.		 0x0
11 R/W Completion Timeout Advisory Non-Fatal [CMPTOADV] As per PCIe specification on Error Signaling, the Requester detecting a Completion Timeout is allowed to handle this as an Advisory Non-Fatal Error.
  • 1: Completion Timeout is handled as Advisory Non-Fatal Error.
  • 0: Completion Timeout is handled as normally as a Non-Fatal Error.
 0x1
12 R/W Enable Gen12 Enhanced Deskew With Skip [ENG12SK]
  • 0: In Gen1/2, Deskew based on TS1/TS2 COM method. Deskew limit up to seven symbols.
  • 1: In Gen1/2, Deskew based on SKIP OS method. Deskew limit up to 20 symbols.
 0x0
22:13 R/W Maximum NP Outstanding Request Limit [MAXNPREQ] The Controller supports 256 outstanding NP requests that can be initiated by the User. However, the number of split completion TLPs that can be stored in the Controller is limited to 128. The Completion FIFO will overflow if more than 128 split completion packets are pending. If the User interface can accept inbound Posted and Completion packets at the samerate as received from PCIe link, then the split completion FIFO will never reach the FULL condition. However, if the User cannot guarantee this, then this register needs to be programmed as described in the Programming Guide section of the Controller User guide. The Controller will limit the maximum number of outstanding NP requests to the value programmed in this register.
Example:
  • 8: Controller will limit maximum number of outstanding NP requests to 8.
  • 0–7: Reserved Default Value is 256.
 10'd128
23 R/W Enable Variable Core Clock [VARCCLKEN] If this bit is set the CORE_CLK input can be driven with Variable Clock depending on the Link Speed, similar to the PIPE_PCLK. 0x0
24 R/W MSI Mask Change Enhanced Interrupt Enable [MSIMSKEN] By default, the Controller provides a single status bit when any function's MSI Mask is programmed or configured by Local firmware or Host SW. Controller also implements an enhanced MSI Mask Interrupt mechanism, which provides per-function set/clear status when a function's MSI Mask is updated by SW. This Local Management programmable bit allows user to choose between the Default and Enhanced MSI Mask Change Interrupt mechanisms. 0x0
25 R/W MSIX Function Mask Change Enhanced Interrupt Enable [MSIXMSKEN] By default, the Controller provides a single status bit when any function's MSIX Function Mask is programmed or configured by Local firmware or Host SW. Controller also implements an enhanced MSIX Function Mask Interrupt mechanism, which provides per-function set/clear status when a function's MSIX Function Mask is updated by SW. This Local Management programmable bit allows user to choose between the Default and Enhanced MSIX Function Mask Change Interrupt mechanisms. 0x0
26 R Reserved [R26] Reserved 0x0
27 R/W Disable Tx Nullify on E2E Parity Error [DTAE2EP] By default, when End-to-End Parity error is detected on inbound/outbound data streams, then all the transmitted outbound packets will be Nullified by the Controller. This bit can be used to turn off nullifying Tx packets on End-to-End Parity Error. 0x0
28 R/W Disable FLR Termination Resp Block [DFLRTRB]
  • 1 : NP Termination due to FLR/Completion Timeout is delayed till the RX Completion FIFO is Empty.
  • 0 : NP Termination due to FLR is done immediately on receiving FLR/Completion Timeout.
 1'b1
29 R/W Disable Rx RAM freeze Uncorrectable Error [DRXRMFR] By default, when an Uncorrectable error is detected on a receive FIFO RAM, then no packets are read out of the RAM subsequent to the error and the RAMs are frozen.
  • 0: Receive FIFO RAMs are frozen after an uncorrectable error.
  • 1: Receive FIFO RAMs continue to read subsequent packets after an uncorrectable error.
 0x0
30 R Reserved [R30] Reserved 0x0
31 R/W HOT Reset Level Trigger [HRLT] If set this bit makes the HOT_RESET_OUT signal behave as a level signal rather than a pulse. When set, the HOT_RESET_OUT will be asserted as long as the controller is in the HOT Reset state. 0x0