PCI Express Device Control and Status Register @0xc8
This register contains control and status bits associated with the device.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/W | Enable Correctable Error Reporting [ECER] | This bit is used to gate the CORRECTABLE_ERROR_OUT output of the Controller in Root Port mode. When a Correctable and Unmasked Error is detected Internally or when a ERR_CORR message is received by the Controller, in Root Port mode, this bit gates the assertion of CORRECTABLE_ERROR_OUT output. | 0x0 |
| 1 | R/W | Enable Non- Fatal Error Reporting [ENFER] | This bit is used to gate the NON_FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 0 is detected Internally or when a ERR_NON_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of NON_FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of NON_FATAL_ERROR_OUT. | 0x0 |
| 2 | R/W | Enable Fatal Error Reporting [EFER] | This bit is used to gate the FATAL_ERROR_OUT output of the Controller in Root Port mode. When an Uncorrectable, Unmasked Error with Uncorrectable Error Severity set to 1 is detected Internally or when a ERR_FATAL message is received by the Controller, in Root Port mode, this bit gates the assertion of FATAL_ERROR_OUT output. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT. | 0x0 |
| 3 | R/W | Enable Unsupported Request Reporting [EURR] | This bit is used to gate the CORRECTABLE_ERROR_OUT, NON_FATAL_ERROR_OUT, FATAL_ERROR_OUT output in Root Port mode on receiving unsupported requests. Note: Alternately, the SERR Enable bit in the Command Register can also be set to enable assertion of FATAL_ERROR_OUT on receiving uncorrectable unsupported requests. | 0x0 |
| 4 | R/W | Enable Relaxed Ordering [ERO] | When set, this bit indicates that the device is allowed to set the Relaxed Ordering bit in the Attributes field of transactions initiated from it when the transactions do not require Strong Ordering. | 0x1 |
| 7:5 | R/W | Max Payload Size [MP] | Specifies the maximum TLP payload size configured. The device must be able to receive a TLP of this maximum size, and should not generate TLP's larger than this value. Software must set this field based on the maximum payload size in the Device Capabilities Register, and the capability of the other side. | 0x0 |
| 8 | R/W | Extended Tag Enable [ETE] | When Set, this bit enables a Function to use an 8- bit Tag field as a Requester. If the bit is Clear, the Function is restricted to a 5-bit Tag field. | 0x1 |
| 9 | R | phantum functions enable [PFE] | Hardwired to 0. | 0x0 |
| 10 | R | aux power PM enable [APPME] | Hardwired to 0. | 0x0 |
| 11 | R/W | Enable no snoop [ENS] | If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency. | 0x1 |
| 14:12 | R/W | Max Read Request Size [MRR] | Specifies the maximum size allowed in read requests generated by the device. | 3'b010 |
| 15 | R | Reserved [R7] | Hardwired to 0. | 0x0 |
| 16 | R/WOCLR | Correctable Error Detected [CED] | Set to 1 by the Controller when it detects a correctable error, regardless of whether the error is masked. | 0x0 |
| 17 | R/WOCLR | Non-Fatal Error Detected [NFED] | Set to 1 by the Controller when it detects a non- fatal error, regardless of whether the error is masked. | 0x0 |
| 18 | R/WOCLR | Fatal Error Detected [FED] | Set to 1 by the Controller when it detects a fatal error, regardless of whether the error is masked. | 0x0 |
| 19 | R/WOCLR | Unsupported Request Detected [URD] | Set to 1 by the Controller when it receives an unsupported request. | 0x0 |
| 20 | R | Aux Power Detected [APD] | Set when auxiliary power is detected by the device. This is an unused field. | 0x0 |
| 21 | R | Transaction Pending [TP] | Indicates if any of the Non-Posted requests issued by the RC are still pending. | 0x0 |
| 31:22 | R | Reserved [R8] | (no description) | 0x0 |