Lane Margining at Receiver Parameters 2 Register @0xcd4
The Lane Margining at Receiver Parameters of the PHY are advertised in this Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 5:0 | R/W | MSamplingRateVoltage [MSRV] | The ratio of bits tested to bits received during voltage margining. A value of 0 is a ratio of 1:64 (1 bit of every 64 bits received), and a value of 63 is a ratio of 64:64 (all bits received). | 0x0 |
| 11:6 | R/W | MSamplingRateTiming [MSRT] | The ratio of bits tested to bits received during timing margining. A value of 0 is a ratio of 1:64 (1 bit of every 64 bits received), and a value of 63 is a ratio of 64:64 (all bits received). | 0x0 |
| 16:12 | R/W | M MaxLanes [MML] | Maximum number of Lanes minus 1 that can be margined at the
same time. It is recommended that this value be greater than or
equal to the number of Lanes in the Link minus 1. Encoding Behavior
is undefined if software attempts to margin more than MMaxLanes+1
at the same time. Note:This value is permitted to exceed the number of Lanes in the Link minus 1. |
0x0 |
| 31:17 | R | Reserved [RES1] | Reserved | 0x0 |