Link Control and Status 2 Register @0xf0
This register contains control and status bits specific to the PCI Express link.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R/W | Target Link Speed [TLS] | This field sets the target speed when the software forces the link into Compliance mode by setting the Enter Compliance bit in this register (0001 = 2.5 GT/s, 0010 = 5 GT/s, 0011 = 8 GT/s, 0100 = 16 GT/s ). The default value of this field is 0001 (2.5 GT/s) when the PCIE_GENERATION_SEL[1:0] strap pins of the Controller are set to 000, 0010 (5 GT/s) when the strap is set to 001, and 0011 (8 GT/s) when the strap pin is set to 010 , and 0100 (16 GT/s) when the strap pin is set to 011. STICKY. | 0x4 |
| 4 | R/W | Enter Compliance [EC] | This bit is used to force the Endpoint device to enter the Compliance mode. Software sets this bit to 1 and initiates a hot reset to force the device into the Compliance mode. The target speed for the Compliance mode is determined by the Target Link Speed field of this register. STICKY. | 0x0 |
| 5 | R/W | Hardware Autonomous Speed Disable [HASD] | When this bit is set, the LTSSM is prevented from changing the operating speed of the link, other than reducing the speed to correct unreliable operation of the link. STICKY. | 0x0 |
| 6 | R/W | Selectable De-Emphasis [SD] | This bit selects the de-emphasis level when the Controller is operating at 5 GT/s (0 = -6 dB, 1 = -3.5 dB). | 0x0 |
| 9:7 | R/W | Transmit Margin [TM] | This field is intended for debug and compliance testing purposes only. It controls the non-de-emphasized voltage level at the transmitter outputs. Its encodings are: 000 = Normal operating range, 001 = 800 – 1200 mV for full swing and 400 – 700 mV for half swing, 010 – 111 = See PCI Express Base Specification 2.0. This field is reset to 0 when th LTSSM enters the Polling.Configuration substate during link training. STICKY. | 0x0 |
| 10 | R/W | Enter Modified Compliance [EMC] | This field is intended for debug and compliance testing purposes only. If this bit is set to 1, the device will transmit the Modified Compliance Pattern when the LTSSM enters the Polling.Compliance substate. STICKY. | 0x0 |
| 11 | R/W | Compliance SOS [CS] | When this bit is set to 1, the device will transmit SKP ordered sets between compliance patterns. STICKY. | 0x0 |
| 15:12 | R/W | Compliance De-Emphasis [CD] | This bit sets the de-emphasis level (for 5 GT/s operation) or the Transmitter Preset level (for 8 GT/s or 16 GT/s operation) when the LTSSM enters the Polling.Compliance state because of software setting the Enter Compliance bit in this register. It is used only when the link is running at either 5 GT/s, 8 GT/s, or 16 GT/s. At 5 GT/s, the only valid settings are 0 (-6 dB) and 1 (-3.5 dB). STICKY. | 0x0 |
| 16 | R | Current De-Emphasis Level [CDEL] | This status bit indicates the current operating de-emphasis level of the transmitter (0 = -6dB, 1 = -3.5dB). | 0x1 |
| 17 | R | Equalization 8.0 GT/s Complete [EQC] | This bit, when set to 1, indicates that the Transmitter Equalization procedure has completed. STICKY. | 0x0 |
| 18 | R | Equalization 8.0 GT/s Phase 1 Successful [EP1S] | This bit, when set to 1, indicates that the Phase 1 of the Transmitter Equalization procedure has completed successfully. STICKY. | 0x0 |
| 19 | R | Equalization 8.0 GT/s Phase 2 Successful [EP2S] | This bit, when set to 1, indicates that the Phase 2 of the Transmitter Equalization procedure has completed successfully. STICKY. | 0x0 |
| 20 | R | Equalization 8.0 GT/s Phase 3 Successful [EP3S] | This bit, when set to 1, indicates that the Phase 3 of the Transmitter Equalization procedure has completed successfully. STICKY. | 0x0 |
| 21 | R/WOCLR | Link Equalization Request 8.0 GT/s [LE] | When the Controller (RP) receives an 8 GTs equalization request from an Upstream Port the Controller internally sets this bit to 1 (i.e., when RP is in the Recovery.RcvrCfg state and receives eight consecutive TS2 Ordered Sets with the Request Equalization bit set to 1b). The LOCAL_INTERRUPT output is also asserted if Link Equalization Request Interrupt Enable is enabled. | 0x0 |
| 22 | R | Retimer Presence Detected [RTP] | When set to 1b, this bit indicates that a Retimer was present during the most recent Link negotiation. | 0x0 |
| 23 | R | Two Retimers Presence Detected [TWRTP] | When set to 1b, this bit indicates that two Retimers were present during the most recent Link negotiation. | 0x0 |
| 27:24 | R | Reserved [R21] | Reserved | 0x0 |
| 30:28 | R | Downstream Component Presence [DCP] | DRS is not supported by the Controller, hence this field is not implemented. | 0x0 |
| 31 | R | DRS Message Received [DMR] | DRS is not supported by the Controller, hence this field is not implemented. | 0x0 |