Link Control and Status Register @0xd0
This register contains control and status bits specific to the PCI Express link. All the read-write bits in this register can also be written from the local management bus.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 1:0 | R/W | Active State Power Management Control [ASPMC] | Controls the level of ASPM support on the PCI Express link associated with this Function. The valid setting are 00: ASPM disabled 01: L0s entry enabled, L1 disabled 10: L1 entry enabled, L0s disabled 11: Both L0s and L1 enabled. | 0x0 |
| 2 | R | Reserved [R6] | Reserved | 0x0 |
| 3 | R/W | Read Completion Boundary (RCB) | Indicates the Read Completion Boundary of the Root Port connected to this Endpoint (0 = 64 bytes, 1 = 128 bytes). This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 4 | R | Link Disable [LD] | Writing a 1 to this bit position causes the LTSSM to go to the Disable Link state. The LTSSM stays in the Disable Link state while this bit is set. Reserved for Endpoint mode. | 0x0 |
| 5 | R | Retrain Link [RL] | Setting this bit to 1 causes the LTSSM to initiate link training. Reserved for Endpoint mode. This bit always reads as 0 | 0x0 |
| 6 | R/W | Common Clock Configuration [CCC] | A value of 0 indicates that the reference clock of this device is asynchronous to that of the upstream device. A value of 1 indicates that the reference clock is common. | 0x0 |
| 7 | R/W | Extended Synch [ES] | Set to 1 to extend the sequence of ordered sets transmitted while exiting from the L0S state. | 0x0 |
| 8 | R | Enable Clock Power Management [ECPM] | When this bit is set to 1, the device may use the CLKREQ# pin on the PCIe connector to power manage the Link clock. This bit is writeable only when the Clock Power Management bit in the Link Capability Register is set to 1. | 0x0 |
| 9 | R/W | Hardware Autonomous Width Disable [HAWD] | When this bit is set, the local application must not request to change the operating width of the link other than attempting to correct unreliable Link operation by reducing Link width. | 0x0 |
| 10 | R | Link Bandwidth Management Interrupt Enable [LBMIE] | When set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0. Not applicable to Endpoints where field is hardwired to 0. | 0x0 |
| 11 | R | Link Autonomous Bandwidth Interrupt Enable [LABIE] | When set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. This enables an interrupt to be generated through PHY_INTERRUPT_OUT if triggered. Hardwired to 0 if Link Bandwidth Notification Capability is 0. Not applicable to Endpoints where field is hardwired to 0. | 0x0 |
| 15:12 | R | Reserved [R15_12] | Reserved | 0x0 |
| 19:16 | R | Negotiated Link Speed [NLS] | Negotiated link speed of the device. The only supported speed ids are 2.5 GT/s per lane (0001), 5.0 GT/s per lane (0010), 8.0 GT/s per lane (0011), and 16.0 GT/s per lane (0100). | 0x4 |
| 25:20 | R | Negotiated Link Width [NLW] | Set at the end of link training to the actual link width negotiated between the two sides. Value is undefined if this registers is accessed before link training. | 0x4 |
| 26 | R | Reserved [R8] | Reserved | 0x0 |
| 27 | R | Link Training Status [LTS] | This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/ Recovery state. Not applicable to Endpoints where field is hardwired to 0. | 0x0 |
| 28 | R | Slot Clock Configuration [SCC] | This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a reference clock on the connector, this bit must be clear. For PF0, this bit can also be written from the local management bus. | 0x0 |
| 29 | R | Data Link Layer Active [DLLA] | Indicates the status of the Data Link Layer. Set to 1 when the DL Control and Management State Machine has reached the DL_Active state. This bit is hardwired to 0 in this version of the Controller. | 0x0 |
| 30 | R/WOCLR | Link Bandwidth Management Status [LBMS] | This bit is set by hardware to indicate that either link training has completed following write to retrain link bit, or when HW has changed link speed or width to attempt to correct unreliable link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0. Not applicable to Endpoints where field is hardwired to 0. | 0x0 |
| 31 | R/WOCLR | Link Autonomous Bandwidth Status [LABS] | This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width, without the Port transitioning through DL_Down status, for reasons other than to attempt to correct unreliable Link operation. This triggers an interrupt to be generated through PHY_INTERRUPT_OUT if enabled. Hardwired to 0 if Link Bandwidth Notification Capability is 0. Not applicable to Endpoints where field is hardwired to 0. | 0x0 |