Local Error and Status Register @0x20c

This register contains the status of the various events, errors, and abnormal conditions in the Controller. Any of the status bits can be reset by writing a 1 into the bit position. This register does not capture any errors signaled by remote devices using PCIe error messages when the Controller is operating in the RC mode. Unless masked by the setting of the Local Interrupt Mask Register, the occurrence of any of these conditions causes the Controller to activate the LOCAL_INTERRUPT output.

Table 1. i_local_error_status_register
Bits SW Name Description Reset
0 R/WOCLR PNP RX FIFOParity Error [PRFPE] Parity error detected while reading from the PNP Receive FIFO RAM. 0x0
1 R/WOCLR Completion RX FIFO Parity Error [CRFPE] Parity error detected while reading from the Completion Receive FIFO RAM. 0x0
2 R/WOCLR Replay RAM Parity Error [RRPE] Parity error detected while reading from Replay Buffer RAM. 0x0
3 R/WOCLR PNP RX FIFOOverflow [PRFO] Overflow occurred in the PNP Receive FIFO. 0x0
4 R/WOCLR Completion RX FIFO Overflow [CRFO] Overflow occurred in the Completion Receive FIFO. 0x0
5 R/WOCLR Replay Timeout [RT] Replay timer timed out. 0x0
6 R/WOCLR Replay Timer Rollover [RTR] Replay timer rolled over after four transmissions of the same TLP. 0x0
7 R/WOCLR Phy Error [PE] Phy error detected on receive side. This bit is set when an error is detected in the receive side of the Physical Layer of the Controller (e.g., a bit error or coding violation). This bit is set upon any of the following errors:
  • PHY reported 8B10B error, Disparity Error, Elastic Buffer Overflow Error, Underflow Error
  • GEN3 TLP, DLLP Framing Errors
  • OS Block Received Without EDS
  • Data Block Received After EDS
  • Illegal OS Block After EDS
  • OS Block Received After SKIP OS
  • OS Block Received After SDS
  • Sync Header Error
  • Loss of Gen3 Block Alignment. This error is not Function-specific.
 0x0
8 R/WOCLR Malformed TLP Received [MTR] Malformed TLP received from the link. 0x0
9 R/WOCLR Unexpected Completion Received [UCR] Unexpected Completion received from the link. 0x0
10 R/WOCLR Flow Control Error [FCE] An error was observed in the flow control advertisements from the other side. 0x0
11 R/WOCLR Completion Timeout [CT] A request timed out waiting for completion. 0x0
12 R Reserved [R12] Reserved 0x0
16:13 R Reserved [R13] Reserved 0x0
17 R/WOCLR End to End Parity Error [EEPE] The Controller detected an End-to-End Parity Error. 0x0
18 R/WOCLR Unmapped TC [UTC] Unmapped TC error. This bit is tied to 0 since this configuration of the Controller does not implement the Virtual Channel Capability Registers. 0x0
19 R/WOCLR MSI Mask Value Change [MMVC] This status bit is set whenever the MSI mask register value in the MSI capability register changes value in ANY of the functions in the controller. 0x0
20 R Reserved [R22] Reserved 0x0
21 R/WOCLR Hardware Autonomous Width Change Disable Toggle [HAWCD] This interrupt status bit indicates that the Host toggled the Hardware Autonomous Width Change bit in the Link Control Register through a Config Write. Upon this interrupt, the Client firmware must read the Link Control Register to check the value set by Host in the Hardware Autonomous Width Change bit. The Host Software may disable autonomous width change by setting Hardware Autonomous Width Disable bit in the Link Control register. If disabled by the Host and if the Endpoint firmware had initiated an autonomous width downsizing prior to this interrupt, then the local Client firmware is responsible to upconfigure the Link to go to its full functional width by initiating the link_upconfigure_retrain_link within 1 ms of this interrupt. 0x0
22 R Reserved [R23_1] Reserved 0x0
24:23 R Reserved [R24] Reserved 0x0
25 R/WOCLR MSIX Function Mask Change [MSIXMSKST] This interrupt status bit is used when MSIX Function Mask Enhanced Interrupt Enable bit is set to 0 by the User. This status bit indicates that the MSIX Function Mask bit of any function, PF or VF, was programmed or configured by Local Firmware Or Host SW. 0x0
27:26 R Reserved [R27] Reserved 0x0
28 R Reserved [R28] Reserved 0x0
29 R/WOCLR axi master read FIFO ram ecc uncorrectable error [AXIMASTER_RFIFO_ER_UN] This indicates an uncorrectable axi master write FIFO ram parity/ecc error. 0x0
30 R/WOCLR axi slave write FIFO ram ecc uncorrectable error [AXISLAVE_WFIFO_ER_UN] This indicates an uncorrectable axi slave write FIFO ram parity/ecc error. 0x0
31 R/WOCLR AXI slave reorder RAM ECC uncorrectable error [REORDER_ER_UN] This indicates an uncorrectable axi slave reorder ram parity/ecc error. 0x0