PCI Express Capability List Register @0xc0
This location identifies the PCI Express device type and its capabilities. It also contains the Capability ID for the PCI Express Structure and the pointer to the next capability structure.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 7:0 | R | Capability ID [CID] | Specifies Capability ID assigned by PCI SIG for this structure. This field is hardwired to 10 hex. | 0x010 |
| 15:8 | R | Next Capability Pointer [NCP] | Points to the next PCI capability structure. Set to 0 because this is the last capability structure. | 0x0 |
| 19:16 | R | Capability Version [PCV] | Identifies the version number of the capability structure. This field is set to 2 by default to indicate that the Controller is compatible to PCI Express Base Specification Revision 3.0. Can be modified using local management interface after asserting input signal MGMT_TYPE1_CONFIG_REG_ACCESS high. | 0x2 |
| 23:20 | R | Device Type [DT] | Indicates the type of device implementing this Function. This field is hardwired to 4 in the RP mode. | 0x4 |
| 24 | R | Slot Implemented [SI] | When Set, this bit indicates that the Link associated with this Port is connected to a slot | 1'b1 |
| 29:25 | R | Interrupt Message Number [IMN] | Identifies the MSI or MSI-X interrupt vector for the interrupt message generated corresponding to the status bits in the Slot Status Register, Root Status Register, or this capability structure. This field must be defined based on the chosen interrupt mode - MSI or MSI-X. This field is hardwired to 0. | 0x0 |
| 30 | R | TCS Routing Supported [TRS] | When set to 1, this bit indicates that the device supports routing of Trusted Configuration Requests. Not valid for Endpoints. Hardwired to 0. | 0x0 |
| 31 | R | Reserved [R0] | Reserved | 0x0 |