Physical Layer Configuration Register 0 @0x0

This register contains the configured parameters at the Physical Layer of the link, and status information from the Physical Layer.

Table 1. i_pl_config_0_reg
Bits SW Name Description Reset
0 R Link Status [LS] Current state of link (1 = link training complete, 0 = link training not complete). 0x0
2:1 R Negotiated Lane Count [NLC] Lane count negotiated with other side during link training (00 = x1, 01 = x2, 10 = x4, 11 = x8). 0x2
4:3 R Negotiated Speed [NS] Current operating speed of link (00 = 2.5G, 01 = 5G, 10 = 8G, 11 = 16G ). 0x0
5 R Link Training Direction [LTD] The state of this bit indicates whether the Controller completed link training as an upstream port(Endpoint)(=0) or a downstream port(Root Port)(=1). Default value depends on CORE_TYPE strap pin. 0x1
6 R/W Phy Error Reporting [APER] This bit controls the reporting of Errors Detected by the PHY. The Errors Detected by the PHY include:
  • Received errors indicated on PIPE RxStatus interface
  • 8.0 GT/s Invalid Sync Header received error
  • 16.0 GT/s Invalid Sync Header received error
If PHY Error Reporting bit is set to 0, the Controller will only report those errors that caused a TLP or DLLP to be dropped because of a Detected PHY Error. If PHY Error Reporting bit is set to 1, the Controller will report all Detected PHY Errors regardless of whether a TLP or DLLP was dropped. The following registers report PHY error in conjunction with this bit:
  • Correctable Error Status Register, i_corr_err_status, bit-0, Receiver Error Status
  • Local Error and StatusRegister, i_local_error_status_register, bit-7, Phy Error
In addition to the Errors Detected by the PHY(PCS), the Controller detects the following Physical Layer Protocol Framing Errors:
  • Framing Errors in the received DLLP and TLP
  • Ordered Set Block Received Without EDS
  • Data Block Received After EDS
  • Illegal Ordered Set Block Received After EDS
  • Ordered Set Block Received After Skip OS
Note: These Errors are always reported independent of the setting of this bit.		 0x0
7 R/W Tx Swing Setting [TSS] This bit drives the PIPE_TX_SWING output of the Controller. 0x0
15:8 R Received FTS Count for 2.5 GT/s speed [RFC] FTS count received from the other side during link training for use at the 2.5 GT/s link speed. The Controller transmits this many FTS sequences while exiting the L0S state when operating at the 2.5 GT/s speed. 0x0
23:16 R Received Link ID [RLID] Link ID received from other side during link training. 0x0
29:24 R LTSSM State [LTSSM] Current state of the LTSSM. The encoding of the states is given in Appendix C. 0x0
30 R Remote Linkwidth Upconfigure Capability Status [R0] A 1 in this field indicates that the remote node advertised Linkwidth Upconfigure Capability in the training sequences in the Configuration.Complete state when the link came up. A 0 indicates that the remote node did not set the Link Upconfigure bit. 0x0
31 R/W Master Loopback Enable [MLE] When the Controller is operating as a Root Port, setting this to 1 causes the LTSSM to initiate a loopback and become the loopback master. This bit is not used in the Endpoint Mode. 0x0