PCI Express Device Capabilities Register 2 @0xe4
This register is not implemented for Virtual Functions. A read to this address returns the Device Capabilities 2 Register fields of Physical Function 0.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R | Completion Timeout Ranges [CTR] | Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 (10 ms – 250 ms). The actual timeout values are in two programmable local management registers, which allow the timeout settings of the two sub-ranges within Range B to be programmed independently. | 0x02 |
| 4 | R | Completion Timeout Disable Supported [CTDS] | A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This bit is set to 1 by default, but can be re-written independently for each Function from the local management bus. | 0x01 |
| 5 | R | ARI forwarding support [AFS] | ARI forwarding supported. | 0x0 |
| 6 | R | OP routing supported [OPRS] | Atomic OP routing supported. | 0x0 |
| 7 | R | 32-Bit Atomic Op Completer Supported [BAOCS32] | Hardwired to 0. | 0x0 |
| 8 | R | 64-Bit Atomic Op Completer Supported [BAOCS64] | Hardwired to 0. | 0x0 |
| 9 | R | 128-Bit CAS Atomic Op Completer Supported [BAOCS128] | Hardwired to 0. | 0x0 |
| 10 | R | Reserved [R12] | Reserved | 0x0 |
| 11 | R | LTR Mechanism Supported [LMS] | A 1 in this bit position indicates that the Function supports the Latency Tolerance Reporting (LTR) Capability. This bit is set to 1 by default, but can be turned off for all Physical Functions by writing into PF 0. | 0x01 |
| 13:12 | R | TPH Completer Supported [TCS] | These bits, when set, indicate that the Function is capable of serving as a completer for requests with Transaction Processing Hints (TPH). It can be turned off for all Physical Functions by writing into PF 0. Defined Encodings are: 00b TPH and Extended TPH Completer not supported. 01b TPH Completer supported; Extended TPH Completer not supported. 10b Reserved. 11b Both TPH and Extended TPH Completer supported. | 0x01 |
| 15:14 | R | Reserved [R13] | Reserved | 0x0 |
| 16 | R | 10-Bit Tag completer supported. [T10CS] | If set function supports 10-bit completer capability; otherwise, the function does not. This field is identical to the PF value. | 0x1 |
| 17 | R | 10-Bit Tag Requester supported. [T10RS] | If set function supports 10-bit requester capability; otherwise, the function does not. This field reflects the value in SRIOV capability register | 0x0 |
| 19:18 | R | OBFF Supported [OPFFS] | A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill (OBFF) capability using message signaling. | 0x1 |
| 20 | R | Extended Format Field Supported [EXFS] | Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all Physical Functions. | 0x1 |
| 21 | R | End-End TLP Prefix Supported [EEPS] | Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. | 0x1 |
| 23:22 | R | Max End-End TLP Prefixes [MEEP] | Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are: 01b 1 End-End TLP Prefix, 10b 2 End-End TLP Prefixes | 0x1 |
| 31:24 | R | Reserved [R14] | Reserved | 0x0 |