PCI Express Device Capabilities Register @0xc4
This register advertises the capabilities of the PCI Express device.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 2:0 | R | Max Payload Size [MP] | Specifies maximum payload size supported by the device. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 3'b011 |
| 4:3 | R | Phantom Functions Supported [PFS] | This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature. | 0x0 |
| 5 | R | Extended Tag Field Supported [ETFS] | Set when device allows the tag field to be extended from 5 to 8 bits. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x1 |
| 8:6 | R | Acceptable L0S Latency [AL0L] | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 11:9 | R | Acceptable L1 Latency [AL1L] | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 0x0 |
| 14:12 | R | Reserved [R3] | Reserved | 0x0 |
| 15 | R | Role-Based Error Reporting [RER] | Enables role-based errer reporting. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. | 1'b1 |
| 17:16 | R | Reserved [R4] | Reserved | 0x0 |
| 25:18 | R | Captured Slot Power Limit Value [CSP] | Specifies upper limit on power supplied by slot. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. . | 0x0 |
| 27:26 | R | Captured Power Limit Scale [CPLS] | Specifies the scale used by Slot Power Limit Value. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. . | 0x0 |
| 28 | R | Function level reset capability [FLRC] | A value of 1b indicates the Function supports the optional Function Level Reset mechanism | 0x0 |
| 31:29 | R | Reserved [R5] | Reserved | 0x0 |