PCI Express Device Capabilities Register @0xc4
This register advertises the capabilities of the PCI Express device encompassing this Function.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 2:0 | R | Max Payload Size [MPS] | Specifies maximum payload size supported by the device. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 3'b011 |
| 4:3 | R | Phantom Functions Supported [PFS] | This field is used to extend the tag field by combining unused Function bits with the tag bits. This field is hardwired to 00 to disable this feature. | 0x0 |
| 5 | R | Extended Tag Field Supported [ETFS] | Set when device allows the tag field to be extended from 5 to 8 bits. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x1 |
| 8:6 | R | Acceptable L0S Latency [AL0SL] | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L0S to L0. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x4 |
| 11:9 | R | Acceptable L1 Latency [AL1SL] | Specifies acceptable latency that the Endpoint can tolerate while transitioning from L1 to L0. This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x0 |
| 14:12 | R | Reserved [R1] | Reserved | 0x0 |
| 15 | R | Role-Based Error Reporting [RBER] | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x01 |
| 17:16 | R | Reserved [R2] | Reserved | 0x0 |
| 25:18 | R | Captured Slot Power Limit Value [CSPLV] | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x0 |
| 27:26 | R | Captured Power Limit Scale [CPLS] | This field reflects the setting of the corresponding field in the PCIe Device Capability Register of PF 0. | 0x0 |
| 28 | R | FLR Capable [FLRC] | Set when device has Function-Level Reset capability. Hardwired to 1. | 0x01 |
| 31:29 | R | Reserved [R3] | Reserved | 0x0 |