Latency Tolerance Reporting (LTR) Extended Capability Header Register @0x1b8
This register contains the PCI Express Extended Capability ID for the Latency Tolerance Reporting (LTR) Capability, its capability version, and the pointer to the next capability structure. This register is implemented only for Physical Function 0. A read from this address of other Physical Functions configuration space returns all zeroes.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 15:0 | R | PCI Express Extended Capability ID [PECID] | This field is hardwired to the Capability ID assigned by PCI SIG to the Latency Tolerance Reporting Capability (0018 hex). | 0x018 |
| 19:16 | R | Capability Version [CV] | Specifies the SIG assigned value for the version of the capability structure. This field is set by default to 1, but can be modified from the local management bus. | 0x01 |
| 31:20 | R | Next Capability Offset [NCO] | Indicates offset to the next PCI Express capability structure. The default next pointer value is dynamic and is dependent on whether the strap or LMI bits are set. | 12'h1c0 |