Uncorrectable Error Status Register @0x104
This register provides the status of the various uncorrectable errors detected by the PCI Express Controller. Software may clear any error bit by writing a 1 into the corresponding bit position. The states of the bits in the Uncorrectable Error Mask Register have no effect on the status bits of this register. In the case of certain errors detected by the Transaction Layer, the associated TLP header is logged in the Header Log Registers.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | Link Training Error status [LTE] | This error indicates that link training is not successful and transition back to detect state. This Status bit is set on any LTSSM transition from Configuration to Detect or Recovery to Detect. | 0x0 |
| 3:1 | R | Reserved [R25] | (no description) | 0x0 |
| 4 | R/WOCLR | Data Link Protocol Error Status [DLPE] | This bit is set when the Controller receives an Ack or Nak DLLP whose sequence does not correspond to that of an unacknowledged TLP or that of the last acknowledged TLP (for details, refer to the PCI Express Base Specifications). | 0x0 |
| 5 | R/WOCLR | Surprise down error status [SDES] | This error status indicates Link up to Link down event. So Status bit is set upon LINK_DOWN_RESET_OUT event and if Surprise down Cap is enabled. | 0x0 |
| 11:6 | R | Reserved [R26] | Reserved | 0x0 |
| 12 | R/WOCLR | Poisoned TLP Status [PT] | This bit is set when the Controller receives a poisoned TLP from the link. This error is considered non-fatal by default. The header of the received TLP with error is logged in the Header Log Registers. | 0x0 |
| 13 | R/WOCLR | Flow Control Protocol Error Status [FCPE] | This bit is set when certain violations of the flow control protocol are detected by the Controller. | 0x0 |
| 14 | R/WOCLR | Completion Timeout Status [CT] | This bit is set when the completion timer associated with an outstanding request times out. This error is considered non-fatal by default. | 0x0 |
| 15 | R/WOCLR | Completer Abort Status [CA] | This bit is set when the Controller has returned the Completer Abort (CA) status to a request received from the link. This error is considered non-fatal by default, except for the special cases outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers. | 0x0 |
| 16 | R/WOCLR | Unexpected Completion Status [UC] | This bit is set when the Controller has received an unexpected Completion packet from the link. | 0x0 |
| 17 | R/WOCLR | Receiver Overflow Status [RO] | This bit is set when the Controller receives a TLP in violation of the receive credit currently available. | 0x0 |
| 18 | R/WOCLR | Malformed TLP Status [MT] | This bit is set when the Controller receives a malformed TLP from the link. This error is considered fatal by default. The header of the received TLP with error is logged in the Header Log Registers. | 0x0 |
| 19 | R/WOCLR | ECRC Error Status [EE] | This bit is set when the Controller has detected an ECRC error in a received TLP. | 0x0 |
| 20 | R/WOCLR | Unsupported Request Error Status [URE] | This bit is set when the Controller has received a request from the link that it does not support. This error is not Function-specific. This error is considered non-fatal by default, except for the special case outlined in PCI Express Base Specification 2.0. The header of the received request that caused the error is logged in the Header Log Registers. | 0x0 |
| 21 | R | Reserved [R27] | Reserved | 0x0 |
| 22 | R/WOCLR | Uncorrectable Internal Error Status [UIE] | This bit is set when the Controller has detected an internal uncorrectable error (HAL parity error or an uncorrectable ECC error while reading from any of the RAMs). This bit is also set in response to the client signaling an internal error through the input UNCORRECTABLE_ERROR_IN. This error is considered fatal by default. | 0x0 |
| 31:23 | R | Reserved [R28] | Reserved | 0x0 |