Root Control and Capability Register @0xdc

This register controls and identifies PCI Express Root Complex specific parameters.

Table 1. i_root_ctrl_cap

Bits	SW	Name	Description	Reset
0	R/W	System Error on Correctable Error Enable [SECEE]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	0x0
1	R/W	System Error on Non-Fatal Error Enable [SENFEE]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	0x0
2	R/W	System Error on Fatal Error Enable [SEFEE]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	0x0
3	R/W	PME Interrupt Enable [PMEIE]	This field can be read and written from the local management APB bus, but its value is not used within the Controller.	0x0
4	R	CRS Software Visibility Enable [CRSSVE]	This capability is not implemented and this bit is hardwired to 0b.	0x0
31:5	R	Reserved [R27]	Reserved	0x0