Lane Error Status Register @0x308

This register contains one bit per lane indicating the physical-layer error status of the corresponding lane. A 1 indicates that a physical-layer error was detected by the Controller in the corresponding lane. The error can be cleared by writing a 1 into the bit position, either through a Configuration Write transaction from the link or from the local management APB bus.

Table 1. i_lane_error_status

Bits	SW	Name	Description	Reset
3:0	R/WOCLR	Lane Error Status [LES]	Each of these bits indicates the error status for the corresponding lane. STICKY.	0x0
31:4	R	Reserved [R0]	(no description)	0x0