LTSSM Transition Debug Control Register23 @0xf94

This register enables firmware to program two specific LTSSM state transitions to be detected and optionally paused for firmware control.

Table 1. i_ltssm_transition_debug_ctrl_reg23
Bits SW Name Description Reset
0 R/W LTSSM State Transition 2 Freeze Enable [LST2FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 2 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 2. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 2. LTSSM will continue to next legal state.
 0x0
1 R/W LTSSM State Transition 2 Check Enable [LST2CHEN] This bit enables the LTSSM transition 2 check.
  • 1: LTSSM State transition 2 check is enabled.
  • 0: LTSSM State transition 2 check is disabled.
 0x0
8:2 R/W Current LTSSM State 2 [CLTST2] This is the 7-bit Current LTSSM State of LTSSM transition 2 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
15:9 R/W Previous LTSSM State 2 [PLTST2] This is the 7-bit Previous LTSSM State of LTSSM transition 2 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
16 R/W LTSSM State Transition 3 Freeze Enable [LST3FREN] This bit can be used by firmware to freeze the LTSSM after the programmed LTSSM transition 3 occurs.
  • 1: LTSSM State will be frozen after the programmed transition 3. LTSSM will stay in current_state, by dropping all OS being received.
  • 0: LTSSM State will not be frozen after the programmed transition 3. LTSSM will continue to next legal state.
 0x0
17 R/W LTSSM State Transition 3 Check Enable [LST3CHEN] This bit enables the LTSSM transition 1 check.
  • 1: LTSSM State transition 3 check is enabled.
  • 0: LTSSM State transition 3 check is disabled.
 0x0
24:18 R/W Current LTSSM State 3 [CLTST3] This is the 7-bit Current LTSSM State of LTSSM transition 3 that is required to be checked and optionally paused. Please refer to the 7-bit LTSSM Encoding table for details. 0x0
31:25 R/W Previous LTSSM State 3 [PLTST3] This is the 7-bit Previous LTSSM State of LTSSM transition 3 that is required to be checked. Please refer to the 7-bit LTSSM Encoding table for details. 0x0