MSI Mask Set Status 3 Register @0xd34
This status register has one bit per function. Each function has a 32-bit MSI Mask. If any bit in the function's MSI Mask register is configured from 0 to 1, then the corresponding function's status bit in this register is set. Local Firmware needs to clear this register by writing a 1.
Each bit is set only when the MSI Mask Change Enhanced Interrupt Enablebit is set by the User in debug_mux_control_2_reg. When this status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked inlocal_intrpt_mask_2_reg. Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | VF60 MSI Mask Set Status [VF60MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF60 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 1 | R/WOCLR | VF61 MSI Mask Set Status [VF61MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF61 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 2 | R/WOCLR | VF62 MSI Mask Set Status [VF62MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF62 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 3 | R/WOCLR | VF63 MSI Mask Set Status [VF63MSIMSKCLST] | Each VF has a 32-bit MSI Mask. This status bit is set when any of the 32-bits in VF63 MSI Mask is programmed or configured from 0 to 1 by Local Firmware Or Host SW. | 0x0 |
| 31:4 | R | Reserved [R31] | Reserved | 0x0 |