MSIX Function Mask Set Status 1 Register @0xd1c
This status register has one bit per function. Each function has a 1-bit MSIX Function Mask. If the function's MSIX Function Mask register is configured from 0 to 1, then the corresponding function's status bit in this register is set. Local Firmware needs to clear this register by writing a 1.
Each bit is set only when the MSIX Function Mask Change Enhanced Interrupt Enable bit is set by the User in debug_mux_control_2_reg. When the status bit is set, the Controller asserts LOCAL_INTERRUPT if not masked in local_intrpt_mask_2_reg. Firmware has to clear this bit in order to deassert LOCAL_INTERRUPT.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 0 | R/WOCLR | PF0 MSIX Function Mask Set Status [PF0MSIXMSKCLST] | Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF0 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 1 | R/WOCLR | PF1 MSIX Function Mask Set Status [PF1MSIXMSKCLST] | Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF1 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 2 | R/WOCLR | PF2 MSIX Function Mask Set Status [PF2MSIXMSKCLST] | Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF2 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 3 | R/WOCLR | PF3 MSIX Function Mask Set Status [PF3MSIXMSKCLST] | Each PF has a 1-bit MSIX Function Mask. This status bit is set when the PF3 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 4 | R/WOCLR | VF0 MSIX Function Mask Set Status [VF0MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF0 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 5 | R/WOCLR | VF1 MSIX Function Mask Set Status [VF1MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF1 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 6 | R/WOCLR | VF2 MSIX Function Mask Set Status [VF2MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF2 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 7 | R/WOCLR | VF3 MSIX Function Mask Set Status [VF3MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF3 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 8 | R/WOCLR | VF4 MSIX Function Mask Set Status [VF4MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF4 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 9 | R/WOCLR | VF5 MSIX Function Mask Set Status [VF5MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF5 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 10 | R/WOCLR | VF6 MSIX Function Mask Set Status [VF6MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF6 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 11 | R/WOCLR | VF7 MSIX Function Mask Set Status [VF7MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF7 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 12 | R/WOCLR | VF8 MSIX Function Mask Set Status [VF8MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF8 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 13 | R/WOCLR | VF9 MSIX Function Mask Set Status [VF9MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF9 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 14 | R/WOCLR | VF10 MSIX Function Mask Set Status [VF10MSIXMSCLSTKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF10 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 15 | R/WOCLR | VF11 MSIX Function Mask Set Status [VF11MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF11 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 16 | R/WOCLR | VF12 MSIX Function Mask Set Status [VF12MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF12 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 17 | R/WOCLR | VF13 MSIX Function Mask Set Status [VF13MSIXMS] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF13 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 18 | R/WOCLR | VF14 MSIX Function Mask Set Status [VF14MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF14 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 19 | R/WOCLR | VF15 MSIX Function Mask Set Status [VF15MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF15 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 20 | R/WOCLR | VF16 MSIX Function Mask Set Status [VF16MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF16 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 21 | R/WOCLR | VF17 MSIX Function Mask Set Status [VF17MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF17 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 22 | R/WOCLR | VF18 MSIX Function Mask Set Status [VF18MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF18 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 23 | R/WOCLR | VF19 MSIX Function Mask Set Status [VF19MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF19 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 24 | R/WOCLR | VF20 MSIX Function Mask Set Status [VF20MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF20 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 25 | R/WOCLR | VF21 MSIX Function Mask Set Status [VF21MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF21 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 26 | R/WOCLR | VF22 MSIX Function Mask Set Status [VF22MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF22 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 27 | R/WOCLR | VF23 MSIX Function Mask Set Status [VF23MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF23 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 28 | R/WOCLR | VF24 MSIX Function Mask Set Status [VF24MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF24 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 29 | R/WOCLR | VF25 MSIX Function Mask Set Status [VF25MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF25 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 30 | R/WOCLR | VF26 MSIX Function Mask Set Status [VF26MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF26 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |
| 31 | R/WOCLR | VF27 MSIX Function Mask Set Status [VF27MSIXMSKCLST] | Each VF has a 1-bit MSIX Function Mask. This status bit is set when the VF27 MSIX Function Mask is programmed or configured from 0 to 1 by local Firmware Or Host SW. | 0x0 |