16 GT/s Lane Equalization Control Register 0 @0x9e0

This register contains the Downstream and Upstream Port 16.0 GT/s Transmitter Preset for lanes 0, 1, 2 and 3 that will be used for 16 GT/s Link Equalization procedure when this port is operating as a Downstream Port.

Table 1. i_pl_16gts_lane_equalization_control_reg0
Bits SW Name Description Reset
3:0 R Lane 0 Downstream Port 16.0 GT/s Transmitter Preset [DPTP016] Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. 0xf
7:4 R Lane 0 Upstream Port 16.0 GT/s Transmitter Preset [UPTP016] 16.0 GT/s Lane 0 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16 GT/s Link Equalization. 0xf
11:8 R Lane 1 Downstream Port 16.0 GT/s Transmitter Preset [DPTP116] Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. 0xf
15:12 R Lane 1 Upstream Port 16.0 GT/s Transmitter Preset [UPTP116] 16.0 GT/s Lane 1 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16 GT/s Link Equalization. 0xf
19:16 R Lane 2 Downstream Port 16.0 GT/s Transmitter Preset [DPTP216] Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. 0xf
23:20 R Lane 2 Upstream Port 16.0 GT/s Transmitter Preset [UPTP216] 16.0 GT/s Lane 2 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16 GT/s Link Equalization. 0xf
27:24 R Lane 3 Downstream Port 16.0 GT/s Transmitter Preset [DPTP316] Transmitter Preset used for 16.0 GT/s equalization by this Port when the Port is operating as a Downstream Port. 0xf
31:28 R Lane 3 Upstream Port 16.0 GT/s Transmitter Preset [UPTP316] 16.0 GT/s Lane 3 Transmitter Preset value that the Downstream Port sends on the associated Lane to the Endpoint device during 16 GT/s Link Equalization. 0xf