Uncorrectable Error Mask Register @0x108

The mask bits in this register control the reporting of uncorrectable errors. For each error type in the Uncorrectable Error Status Register, there is a corresponding bit in this register to mask its reporting. Setting the mask bit has the following effects:

  • The occurrence of the error does not cause activation of the FATAL_ERROR_OUT or NON_FATAL_ERROR_OUT output of the Controller, depending on the severity of the error.
  • The header of the TLP in which the error was detected is not logged in the Header Log Registers.
  • The First Error Pointer in the Advanced Error Capabilities and Control Register is not updated on the detection of the error. The individual bits of the mask register are described below.
Table 1. i_uncorr_err_mask
Bits SW Name Description Reset
0 R/W Link Training Error Mask [LTEM] This bit is set to mask the reporting of Link Training Error Mask. STICKY. 0x0
3:1 R Reserved [R29] Reserved 0x0
4 R/W Data Link Protocol Error Mask [DLPER] This bit is set to mask the reporting of Data Link Protocol Errors. STICKY. 0x0
5 R Surprise Down Error Status Mask [SDESM] This bit is set to mask the reporting of Surprise Down Error Status Mask. STICKY. If surprise down capability is enabled then it can be re-written else it is read only. 0x0
11:6 R Reserved [R30] Reserved 0x0
12 R/W Poisoned TLP Mask [PTM] This bit is set to mask the reporting of a Poisoned TLP. STICKY. 0x0
13 R/W Flow Control Protocol Error Mask [FCPER] This bit is set to mask the reporting of Flow Control Protocol Errors. STICKY. 0x0
14 R/W Completion Timeout Mask [CTM] This bit is set to mask the reporting of Completion Timeouts. STICKY. 0x0
15 R/W Completer Abort Mask [CAM] This bit is set to mask the reporting of the Controller sending a Completer Abort. STICKY. 0x0
16 R/W Unexpected Completion Mask [UCM] This bit is set to mask the reporting of unexpected Completions received by the Controller. STICKY. 0x0
17 R/W Receiver Overflow Mask [ROM] This bit is set to mask the reporting of violations of receive credit. STICKY. 0x0
18 R/W Malformed TLP Mask [MTM] This bit is set to mask the reporting of malformed TLPs received from the link. STICKY. 0x0
19 R/W ECRC Error Mask [EEM] This bit is set to mask the reporting of ECRC errors. STICKY. 0x0
20 R/W Unsupported Request Error Mask [UREM] This bit is set to mask the reporting of unexpected requests received from the link. STICKY. 0x0
21 R Reserved [R31] Reserved 0x0
22 R/W Uncorrectable Internal Error Mask [UIEM] This bit is set to mask the reporting of internal errors. STICKY. 0x1
31:23 R Reserved [R32] Reserved 0x0