Lane Error Status Register @0x308

This register contains one bit per lane indicating the physical-layer error status of the corresponding lane. A 1 indicates that a physical-layer error was detected by the Controller in the corresponding lane. The error can be cleared by writing a 1 into the bit position, either through a Configuration Write transaction from the link or from the local management bus. The following errors are reported in this status bit:

• Parity error detected in Gen3 SKP OS.
• Loss of Block Alignment in the lane.