Slot Capability Register @0xd4

The Slot Capabilities register identifies PCI Express slot specific capabilities.

Table 1. i_slot_capability
Bits SW Name Description Reset
0 R Attention Button Present [ABPRSNT] When Set, this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. 1'b0
1 R Power Controller Present [PCP] When Set, this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). 1'b0
2 R MRL Sensor Present [MRLSP] When Set, this bit indicates that an MRL Sensor is implemented on the chassis for this slot. 1'b0
3 R Attention Indicator Present [AIP] When Set, this bit indicates that an Attention Indicator is electrically controlled by the chassis. 1'b0
4 R Power Indicator Present [PIP] When Set, this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. 1'b0
5 R Hot-Plug Surprise [HPS] When Set, this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the operating system to allow for such removal without impacting continued software operation. 1'b0
6 R Hot-Plug Capable [HPC] When Set, this bit indicates that this slot is capable of supporting hot-plug operations. 1'b0
14:7 R Slot Power Limit Value [SPLV] In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by the slot (se6.9) or by other means to the adapter. Power limit (in Watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field except when the Slot Power Limit Scale field equals 00b (1.0x) and Slot Power Limit Value exceeds EFh, the following alternative encodings are used:
  • F0h = 250 W Slot Power Limit
  • F1h = 275 W Slot Power Limit
  • F2h = 300 W Slot Power Limit
  • F3h to FFh = Reserved for Slot Power Limit values above 300 W.
This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/ firmware initialization is 0000 0000b.		 8'b00000000
16:15 R Slot Power Limit Scale [SPLS] Specifies the scale used for the Slot Power Limit Value. Range of Values:
  • 00b = 1.0x
  • 01b = 0.1x
  • 10b = 0.01x
  • 11b = 0.001x
This register must be implemented if the Slot Implemented bit is Set. Writes to this register also cause the Port to send the Set_Slot_Power_Limit Message. The default value prior to hardware/firmware initialization is 00b.		 2'b00
17 R Electromechanic Interlock Present [EIP] When Set, this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. 1'b0
18 R No Command Completed Support [NCCS] When Set, this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be Set if the hot-plug capable Port is able to accept writes to all fields of the Slot Control register without delay between successive writes. 1'b0
31:19 R Physical Slot Number [PSN] This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis, regardless of the form factor associated with the slot. This field must be initialized to zero for Ports connected to devices that are either integrated on the system board or integrated within the same silicon as the Switch device or Root Port. 13'd0