LTSSM Transition Debug Status Register @0xfa0

This register reflects the Status of the eight LTSSM State Transitions that can be programmed for firmware monitor and control.

Table 1. i_ltssm_transition_debug_stat_reg
Bits SW Name Description Reset
7:0 R/WOCLR LTSSM State Transition Without Freeze Status [LSTWOFR] This field contains status 1-bit for each of the eight programmable LTSSM State transitions.
  • 1: Indicates the programmed LTSSM transition occured and was not programmed to freeze on that transition.
  • 0: Indicates that either the programmed LTSSM transition has not occured or was programmed to freeze. Write 1 to Clear.
0x0
15:8 R/WOCLR LTSSM State Transition With Freeze Status [LSTWFR] This field contains status 1-bit for each of the eight programmable LTSSM State transitions.
  • 1: Indicates the programmed LTSSM transition occured and was programmed to freeze on that transition. LTSSM is frozen at the Current LTSSM State, waiting for firmware intervention to un-freeze.
  • 0: Indicates that either the programmed LTSSM transition has not occured or was not programmed to freeze. Write 1 to Clear.
 0x0
31:16 R Reserved [R16] Reserved 0x0