PCI Express Device Capabilities 2 Register @0xe4

This register advertises the capabilities of the PCI Express device.

Table 1. i_pcie_cap_2
Bits SW Name Description Reset
3:0 R Completion Timeout Ranges [CTR] Specifies the Completion Timeout values supported by the device. This field is set by default to 0010 (10 ms – 250 ms), but can be modified from the local management APB bus. The actual timeout values are in two programmable local management registers, which allow the timeout settings of the two sub-ranges within Range B to be programmed independently. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 4'b0010
4 R Completion Timeout Disable Supported [CTDS] A 1 in this field indicates that the associated Function supports the capability to turn off its Completion timeout. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 1'b1
5 R ARI Forwarding Supported [AFS] A 1 in this bit indicates that the device is able to forward TLPs with function number greater than eight. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x1
6 R Atomic OP routing supported [AOPRS] Applicable only to Switch Upstream Ports, Switch Downstream Ports, and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x0
7 R 32-Bit Atomic Op Completer Supported [ACS32] Hardwired to 0. 0x0
8 R 64-bit Atomic Op Completer Supported [ACS64] Hardwired to 0. 0x0
9 R 128-bit CAS Atomic Op Completer Supported [ACS128] Hardwired to 0. 0x0
10 R Reserved [R14] Reserved 0x0
11 R LTR mechanism supported [LMS] A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x1
12 R TPH Completer Supported [TPHC] These bits, when set, indicate that the Function is capable of serving as a completer for requests with Transaction Processing Hints (TPH). It can be turned off for all Physical Functions by writing into PF 0. Defined Encodings are:
  • 00b TPH and Extended TPH Completer not supported
  • 01b TPH Completer supported; Extended TPH Completer not supported
  • 10b Reserved
  • 11b Both TPH and Extended TPH Completer supported
 0x01
13 R RSVD RSVD 1'h0
15:14 R Reserved [R15] Reserved 0x0
16 R 10-Bit Tag completer supported. [T10CS] If set function supports 1-bit completer capability; otherwise, the function does not. This field can be modified using local management interface. 0x1
17 R 10-Bit Tag Requester supported. [T10RS] If set function supports 1-bit requester capability; otherwise, the function does not. This bit can be disabled using local the management register. 0x0
19:18 R OBFF Supported [OBFF] A 1 in this bit position indicates that the Function supports the Optimized Buffer Flush/Fill (OBFF) capability using message signaling. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x1
20 R Extended Format Field Supported [EXFS] Indicates that the Function supports the 3-bit definition of the Fmt field in the TLP header. This bit is hardwired to 1 for all physical functions. 0x1
21 R End-End TLP Prefix Supported [EEPS] Indicates whether the Function supports End-End TLP Prefixes. A 1 in this field indicates that the Function supports receiving TLPs containing End-End TLP Prefixes. This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write. 0x1
23:22 R Max End-End TLP Prefixes [MEEP] Indicates the maximum number of End-End TLP Prefixes supported by the Function. The supported values are:
  • 01b 1 End-End TLP Prefix
  • 10b 2 End-End TLP Prefixes.
This field can be written from the APB bus by setting [21] bit high of the pcie_mgmt_APB_ADDR during a local management register write.		 0x1
31:24 R Reserved [R16] Reserved 0x0