Link Control3 Register @0x304
Link Control3 Register.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 8:0 | R | Reserved [R1] | Reserved | 0x0 |
| 12:9 | R/W | Enable Lower SKP OS Generation Vector [ELSOSGV] | When the Link is in L0 and the bit in this field corresponding to the current Link speed is Set, SKP Ordered Sets are scheduled at the rate defined for SRNS, overriding the rate required based on the clock tolerance architecture. | 0x0 |
| 31:13 | R | Reserved [R2] | Reserved | 0x0 |