PIPE RX Electrical Idle Glitch Control Register @0xda4
This register controls the behavior of glitch filter on the pipe rx Electrical Idle signal from the PHY/PCS. Adjustment of this register is not required for normal operations.
| Bits | SW | Name | Description | Reset |
|---|---|---|---|---|
| 3:0 | R/W | RX Electrical Idle Glitch Filter Disable [GFLD] | By default controller enables glitch filter on all lanes. Setting this bit to one makes the controller to disable the glitch filter on that corresponding lanes in which the bit is set. When all bits are set to one the Glitch filter is completely bypassed. When any bit is zero glitch filter is enabled, and de-glitching is done only on the lanes that are set to zero. | 0x0 |
| 15:4 | R | Reserved [RSVGFLD] | Reserved | 0x0 |
| 23:16 | R/W | RX Electrical Idle Glitch Filter Count CORE Clocks [GFLCC] | This controls the glitch filter on CORE Clock domain. This counter indicates the number of CORE Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as (CORE Clock Period * Number of CORE Clocks) this delay should be same or close enough for both CORE Clock (GFLCC) and PM Clock (GFLCP). | 0x20 |
| 31:24 | R/W | RX Electrical Idle Glitch Filter Count PM Clocks [GFLCP] | This controls the glitch filter on PM Clock domain. This counter indicates the number of PM Clocks the glitch will be filtered out. The total delay of the glitch filter is calculated as (PM Clock Period * Number of PM Clocks) this delay should be same or close enough for both Core Clock (GFLCC) and PM Clock (GFLCP). | 0x04 |