ASPM L1 Entry Timeout Delay Register @0x48

This register defines the timeout value for transitioning to the L1 power state under Active State Power management. If the transmit side has been idle for this interval, the Controller will initiate a transition of its link to the L1 power state.

Table 1. i_aspm_L1_entry_tmout_delay_reg
Bits SW Name Description Reset
19:0 R/W L1 Timeout [L1T] Contains the timeout value(in units of 16 ns) for transitioning to the L1 power state. Setting it to 0 permanently disables the transition to the L1 power state. 20'd750
30:20 R Reserved [R7] Reserved 0x0
31 R/W Disable Check for LinkRX IDLE [DISLNRXCHK] This bit is used to configure the ASPM L1 Entry mechanism:
  • 1: Link is checked for IDLE only on the TX to determine ASPM L1 Entry. ASPM L1 entry is initiated if no TLP is transmitted for the L1 timeout period.
  • 0: Link is checked for IDLE both on the TX and RX to determine ASPM L1 Entry. ASPM L1 entry is initiated if no TLP is transmitted/received for the L1 timeout period.
 0x0