PHY STATUS 1 Register @0x238

This status register provides additional debug information about the PHY. Bits 8:0 provide information to debug Receiver Errors.

Table 1. i_phy_status_1_reg

Bits	SW	Name	Description	Reset
0	R/WOCLR	TLP PHYError Status [TLPPHYER]	This bit indicates that a PHY Error was detected on the PIPE_RX_STATUS within a TLP. Write a 1 to clear this field.	0x0
1	R/WOCLR	OS Block After Skip OS [OSASKP]	This bit indicates that an Ordered Set BLock was received immediately after a SKIP OS. This is a framing error. Write a 1 to clear this field.	0x0
2	R/WOCLR	Illegal OS BlockAfter EDS [ILOSEDS]	The Valid OS blocks after an EDS are EIOS, EIEOS and SKP. If any other OS blocks are received after EDS, then it is a framing error and this bit is asserted.	0x0
3	R/WOCLR	Data Block After EDS [DATEDS]	This bit is set if a Data Block is received after an EDS. Write a 1 to clear this error.	0x0
4	R/WOCLR	OS Block Received without EDS [OSWOEDS]	This bit is set if an Ordered Set Block is received without an EDS. This is a framing error. Write a 1 to clear this error.	0x0
5	R/WOCLR	Gen3 Framing Error Detected [G3FRERR]	This bit is set if a framing error is detected while receiving a TLP in Gen3. Example, if an invalid token is received in a data stream, this error is flagged. Write a 1 to clear this error.	0x0
6	R/WOCLR	OS Block Received After SDS [OSAFSDS]	This bit is set if an SDS is received after an SDS. This is a framing error. Write a 1 to clear this error.	0x0
7	R/WOCLR	Invalid Sync Header Error [INVSYNHR]	This bit is set if an invalid Sync Header is detected. 00 and 11 are Invalid Sync Headers. Write a 1 to clear this error.	0x0
8	R/WOCLR	Loss of Block Alignment Error [LOSBLKALN]	This bit is set if the PHY Loses Block Alignment during data stream. This is detected based upon an unexpected PIPE_RX_VALID input deassertion during data stream. Write a 1 to clear this error.	0x0
31:9	R	Reserved [R31]	Reserved	0x0