Correctable Error Mask Register @0x114

The mask bits in this register control the reporting of correctable errors. For each error type in the Correctable Error Status Register, there is a corresponding bit in this register to mask its reporting. When a mask bit is set, the occurrence of the error is not reported to the Root Complex (by a PCI Express error message). The individual bits of the mask register are described below. The bits marked RW can also be written from the local management bus.

Table 1. i_corr_err_mask

Bits	SW	Name	Description	Reset
0	R/W	Receiver Error Mask [REM]	This bit, when set, masks the generation of error messages in response to the Physical Layer errors STICKY.	0x0
5:1	R	Reserved [R15]	Reserved	0x0
6	R/W	Bad TLP Mask [BTM]	This bit, when set, masks the generation of error messages in response to a 'Bad TLP' received. STICKY.	0x0
7	R/W	Bad DLLP Mask [BDM]	This bit, when set, masks the generation of error messages in response to a 'Bad DLLP' received. STICKY.	0x0
8	R/W	Replay Number Rollover Mask [RNRM]	This bit, when set, masks the generation of error messages in response to a Replay Number Rollover event. STICKY.	0x0
11:9	R	Reserved [R16]	Reserved	0x0
12	R/W	Replay Timer Timeout Mask [RTTM]	This bit, when set, masks the generation of error messages in response to a Replay Timer timeout event. STICKY.	0x0
13	R/W	Advisory Non-Fatal Error Mask [ANFEM]	This bit, when set, masks the generation of error messages in response to an uncorrectable error occur, which is determined to belong to one of the special cases (as described in Section 6.2.3.2.4 of the PCI Express 2.0 Specifications). STICKY.	0x01
14	R/W	Corrected Internal Error Mask [CIEM]	This bit, when set, masks the generation of error messages in response to a corrected internal error condition. STICKY.	0x01
15	R/W	Header Log Overflow Mask [HLOM]	This bit, when set, masks the generation of error messages in response to a Header Log register overflow. STICKY.	0x01
31:16	R	Reserved [R17]	Reserved	0x0