Root Error Status Register @0x130

This register contains status information on error messages received from the link (that is, errors reported by remote devices attached to this Root Complex).

Table 1. i_root_err_stat

Bits	SW	Name	Description	Reset
0	R/WOCLR	Correctable Error Message Received [ECR]	This bit is set when the RC receives a Correctable error message from the link. STICKY	0x0
1	R/WOCLR	Multiple Correctable Error Messages Received [MECR]	This bit is set when the RC receives a Correctable error message from the link, if the ERR_COR received bit is already set. STICKY	0x0
2	R/WOCLR	Fatal/Non-Fatal Error Message Received [EFNR]	This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link. STICKY	0x0
3	R/WOCLR	Multiple Fatal/ Non-Fatal Error Messages Received [MEFNR]	This bit is set when the RC receives either a Fatal or Non-Fatal error message from the link, and the ERR_FATAL/NONFATAL Received bit is already set. STICKY	0x0
4	R/WOCLR	First Uncorrectable Fatal [FUF]	This bit, when set, indicates that the first Uncorrectable error message received was for a Fatal error. STICKY	0x0
5	R/WOCLR	Non-Fatal Error Messages Received [NEMR]	This bit, when set, indicates that the RC has received one or more Non-Fatal error messages from the link. STICKY	0x0
6	R/WOCLR	Fatal Error Messages Received [FEMR]	This bit, when set, indicates that the RC has received one or more Fatal error messages from the link. STICKY	0x0
31:7	R	Reserved [R45]	Reserved	0x0