Base Address Register 2 @0x18

This is one of the six Base Address Registers defined by the PCI Specifications 3.0. These registers are used to define address ranges for memory and I/O accesses to the Endpoint device. During the initial configuration of the device, the configuration program determines the size of the address range defined by the BAR by writing a pattern of all 1s into the BAR, reading back from the BAR, and noting the position of the first 1 (the most significant) in the returned value. A value of 0 is returned by the Controller if BAR 2 is not configured. Otherwise, the number of 1s returned is based on the size of the BAR. BAR2 can be setup as 32-bit memory or I/O BAR, or can be paired with BAR 3 to form a 64-bit memory BAR. The settings of this BAR is defined in the BAR Configuration Register associated with this PF. The BAR aperture can be controller in two different ways:

1. When the Resizable BAR Capability is enabled, the aperture is controlled by the setting of the BAR width field in Resizable BAR Control Register. The Resizable BAR Capability is enabled by setting the Enable Resizable BAR Capability bit (bit 31) of the associated Physical Function BAR Configuration Register 1.
2. When the Resizable BAR Capability is disabled for the Physical Function, the aperture is controlled by the setting of the PF BAR Configuration Register.